[llvm-branch-commits] [llvm-branch] r115101 - /llvm/branches/release_28/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Bill Wendling]

Author: void
Date: Wed Sep 29 18:07:19 2010
New Revision: 115101

URL: http://llvm.org/viewvc/llvm-project?rev=115101&view=rev
Log:
Merge in r114506.

Modified:
    llvm/branches/release_28/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/branches/release_28/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_28/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=115101&r1=115100&r2=115101&view=diff
==============================================================================
--- llvm/branches/release_28/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/release_28/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Sep 29 18:07:19 2010
@@ -1389,7 +1389,8 @@
 
   // Check that CPSR isn't set between the comparison instruction and the one we
   // want to change.
-  MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+  MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+    B = MI->getParent()->begin();
   --I;
   for (; I != E; --I) {
     const MachineInstr &Instr = *I;
@@ -1403,6 +1404,10 @@
       if (MO.getReg() == ARM::CPSR)
         return false;
     }
+
+    if (I == B)
+      // The 'and' is below the comparison instruction.
+      return false;
   }
 
   // Set the "zero" bit in CPSR.