[llvm-branch-commits] [llvm-branch] r114287 - in /llvm/branches/ggreif/arm-peephole: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h
Gabor Greif
ggreif at gmail.com
Sat Sep 18 08:29:03 PDT 2010
Author: ggreif
Date: Sat Sep 18 10:29:03 2010
New Revision: 114287
URL: http://llvm.org/viewvc/llvm-project?rev=114287&view=rev
Log:
reseat optimization logic to where it belongs; minor generalization on the way
Modified:
llvm/branches/ggreif/arm-peephole/include/llvm/Target/TargetInstrInfo.h
llvm/branches/ggreif/arm-peephole/lib/CodeGen/PeepholeOptimizer.cpp
llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.h
Modified: llvm/branches/ggreif/arm-peephole/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/include/llvm/Target/TargetInstrInfo.h?rev=114287&r1=114286&r2=114287&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/ggreif/arm-peephole/include/llvm/Target/TargetInstrInfo.h Sat Sep 18 10:29:03 2010
@@ -581,7 +581,7 @@
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
virtual bool AnalyzeCompare(const MachineInstr *MI,
- unsigned &SrcReg, int &CmpValue) const {
+ unsigned &SrcReg, int &Mask, int &Value) const {
return false;
}
@@ -589,8 +589,8 @@
/// into something more efficient. E.g., on ARM most instructions can set the
/// flags register, obviating the need for a separate CMP. Update the iterator
/// *only* if a transformation took place.
- virtual bool OptimizeCompareInstr(MachineInstr * /*CmpInstr*/,
- unsigned /*SrcReg*/, int /*CmpValue*/,
+ virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr,
+ unsigned SrcReg, int Mask, int Value,
MachineBasicBlock::iterator &) const {
return false;
}
Modified: llvm/branches/ggreif/arm-peephole/lib/CodeGen/PeepholeOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/CodeGen/PeepholeOptimizer.cpp?rev=114287&r1=114286&r2=114287&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/CodeGen/PeepholeOptimizer.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/CodeGen/PeepholeOptimizer.cpp Sat Sep 18 10:29:03 2010
@@ -238,13 +238,13 @@
// If this instruction is a comparison against zero and isn't comparing a
// physical register, we can try to optimize it.
unsigned SrcReg;
- int CmpValue;
- if (!TII->AnalyzeCompare(MI, SrcReg, CmpValue) ||
+ int CmpMask, CmpValue;
+ if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
TargetRegisterInfo::isPhysicalRegister(SrcReg))
return false;
// Attempt to optimize the comparison instruction.
- if (TII->OptimizeCompareInstr(MI, SrcReg, CmpValue, NextIter)) {
+ if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, NextIter)) {
++NumEliminated;
return true;
}
Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=114287&r1=114286&r2=114287&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.cpp Sat Sep 18 10:29:03 2010
@@ -1374,7 +1374,7 @@
}
bool ARMBaseInstrInfo::
-AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const {
+AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask, int &CmpValue) const {
switch (MI->getOpcode()) {
default: break;
case ARM::CMPri:
@@ -1382,9 +1382,16 @@
case ARM::t2CMPri:
case ARM::t2CMPzri:
SrcReg = MI->getOperand(0).getReg();
+ CmpMask = ~0;
CmpValue = MI->getOperand(1).getImm();
return true;
- case ARM::TSTri: {
+ case ARM::TSTri:
+ SrcReg = MI->getOperand(0).getReg();
+ CmpMask = MI->getOperand(1).getImm();
+ CmpValue = 0;
+ return true;
+ /*
+ {
MachineBasicBlock::const_iterator MII(MI);
if (MI->getParent()->begin() == MII)
return false;
@@ -1398,7 +1405,7 @@
return true;
}
}
- break;
+ break;*/
}
return false;
@@ -1408,8 +1415,8 @@
/// comparison into one that sets the zero bit in the flags register. Update the
/// iterator *only* if a transformation took place.
bool ARMBaseInstrInfo::
-OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue,
- MachineBasicBlock::iterator &MII) const {
+OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
+ int CmpValue, MachineBasicBlock::iterator &MII) const {
if (CmpValue != 0)
return false;
@@ -1420,6 +1427,28 @@
return false;
MachineInstr *MI = &*DI;
+ // Masked compares sometimes use the same register as the corresponding 'and'.
+ if (CmpMask != ~0) {
+ for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(SrcReg),
+ UE = MRI.use_end(); UI != UE; ++UI) {
+ if (UI->getParent() != CmpInstr->getParent()) continue;
+ switch (UI->getOpcode()) {
+ case ARM::ANDri: {
+ MachineInstr &AND = *UI;
+ if (SrcReg == AND.getOperand(1).getReg() &&
+ CmpMask == AND.getOperand(2).getImm()) {
+ SrcReg = AND.getOperand(0).getReg();
+ MI = ∧
+ break;
+ }
+ continue;
+ }
+ default:
+ continue;
+ }
+ break;
+ }
+ }
// Conservatively refuse to convert an instruction which isn't in the same BB
// as the comparison.
Modified: llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.h?rev=114287&r1=114286&r2=114287&view=diff
==============================================================================
--- llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/ggreif/arm-peephole/lib/Target/ARM/ARMBaseInstrInfo.h Sat Sep 18 10:29:03 2010
@@ -326,12 +326,12 @@
/// in SrcReg and the value it compares against in CmpValue. Return true if
/// the comparison instruction can be analyzed.
virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
- int &CmpValue) const;
+ int &CmpMask, int &CmpValue) const;
/// OptimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero".
virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
- int CmpValue,
+ int CmpMask, int CmpValue,
MachineBasicBlock::iterator &MII) const;
virtual unsigned getNumMicroOps(const MachineInstr *MI,
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