[llvm-branch-commits] [llvm-branch] r113540 - in /llvm/branches/release_28: ./ lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/Thumb2SizeReduction.cpp
Bill Wendling
isanbard at gmail.com
Thu Sep 9 13:56:38 PDT 2010
Author: void
Date: Thu Sep 9 15:56:38 2010
New Revision: 113540
URL: http://llvm.org/viewvc/llvm-project?rev=113540&view=rev
Log:
Approved by Evan:
$ svn merge -c 113297 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113297 into '.':
U lib/Target/ARM/Thumb2SizeReduction.cpp
$ svn merge -c 113322 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113322 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMInstrFormats.td
$ svn merge -c 113365 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113365 into '.':
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 113366 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113366 into '.':
G lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 113394 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113394 into '.':
G lib/Target/ARM/ARMBaseRegisterInfo.cpp
Modified:
llvm/branches/release_28/ (props changed)
llvm/branches/release_28/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/release_28/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/release_28/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/release_28/lib/Target/ARM/ARMInstrVFP.td
llvm/branches/release_28/lib/Target/ARM/Thumb2SizeReduction.cpp
Propchange: llvm/branches/release_28/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Sep 9 15:56:38 2010
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Pertwee:110850,110961
-/llvm/trunk:113109,113123,113146,113158,113255,113257,113260,113299,113303,113345,113483-113485
+/llvm/trunk:113109,113123,113146,113158,113255,113257,113260,113297,113299,113303,113322,113345,113365-113366,113394,113483-113485
Modified: llvm/branches/release_28/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_28/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113540&r1=113539&r2=113540&view=diff
==============================================================================
--- llvm/branches/release_28/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/release_28/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Sep 9 15:56:38 2010
@@ -667,8 +667,14 @@
}
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
- return (RealignStack && !AFI->isThumb1OnlyFunction());
+ // We can't realign the stack if:
+ // 1. Dynamic stack realignment is explicitly disabled,
+ // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
+ // 3. There are VLAs in the function and the base pointer is disabled.
+ return (RealignStack && !AFI->isThumb1OnlyFunction() &&
+ (!MFI->hasVarSizedObjects() || EnableBasePointer));
}
bool ARMBaseRegisterInfo::
@@ -1057,8 +1063,11 @@
if (isFixed) {
FrameReg = getFrameRegister(MF);
Offset = FPOffset;
- } else if (MFI->hasVarSizedObjects())
+ } else if (MFI->hasVarSizedObjects()) {
+ assert(hasBasePointer(MF) &&
+ "VLAs and dynamic stack alignment, but missing base pointer!");
FrameReg = BasePtr;
+ }
return Offset;
}
@@ -1068,7 +1077,7 @@
// there are VLAs (and thus the SP isn't reliable as a base).
if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
FrameReg = getFrameRegister(MF);
- Offset = FPOffset;
+ return FPOffset;
} else if (MFI->hasVarSizedObjects()) {
assert(hasBasePointer(MF) && "missing base pointer!");
// Use the base register since we have it.
@@ -1078,12 +1087,12 @@
// out of range references.
if (FPOffset >= -255 && FPOffset < 0) {
FrameReg = getFrameRegister(MF);
- Offset = FPOffset;
+ return FPOffset;
}
} else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
// Otherwise, use SP or FP, whichever is closer to the stack slot.
FrameReg = getFrameRegister(MF);
- Offset = FPOffset;
+ return FPOffset;
}
}
// Use the base pointer if we have one.
@@ -1887,7 +1896,8 @@
AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
- // If we need dynamic stack realignment, do it here.
+ // If we need dynamic stack realignment, do it here. Be paranoid and make
+ // sure if we also have VLAs, we have a base pointer for frame access.
if (needsStackRealignment(MF)) {
unsigned MaxAlign = MFI->getMaxAlignment();
assert (!AFI->isThumb1OnlyFunction());
Modified: llvm/branches/release_28/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_28/lib/Target/ARM/ARMInstrFormats.td?rev=113540&r1=113539&r2=113540&view=diff
==============================================================================
--- llvm/branches/release_28/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/release_28/lib/Target/ARM/ARMInstrFormats.td Thu Sep 9 15:56:38 2010
@@ -1332,9 +1332,9 @@
}
// Load / store multiple
-class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
+class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
- : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
+ : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
VFPLdStMulFrm, itin, asm, cstr, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
let Inst{27-25} = 0b110;
@@ -1344,9 +1344,9 @@
let D = VFPNeonDomain;
}
-class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
+class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
- : VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
+ : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
VFPLdStMulFrm, itin, asm, cstr, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
let Inst{27-25} = 0b110;
Modified: llvm/branches/release_28/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_28/lib/Target/ARM/ARMInstrNEON.td?rev=113540&r1=113539&r2=113540&view=diff
==============================================================================
--- llvm/branches/release_28/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/release_28/lib/Target/ARM/ARMInstrNEON.td Thu Sep 9 15:56:38 2010
@@ -133,7 +133,7 @@
// This is equivalent to VLDMD except that it has a Q register operand
// instead of a pair of D registers.
def VLDMQ
- : AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
+ : AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
@@ -151,7 +151,7 @@
// This is equivalent to VSTMD except that it has a Q register operand
// instead of a pair of D registers.
def VSTMQ
- : AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
+ : AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
[(store (v2f64 QPR:$src), addrmode4:$addr)]>;
Modified: llvm/branches/release_28/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_28/lib/Target/ARM/ARMInstrVFP.td?rev=113540&r1=113539&r2=113540&view=diff
==============================================================================
--- llvm/branches/release_28/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/branches/release_28/lib/Target/ARM/ARMInstrVFP.td Thu Sep 9 15:56:38 2010
@@ -77,19 +77,19 @@
//
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
-def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
+def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
variable_ops), IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
let Inst{20} = 1;
}
-def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
+def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
variable_ops), IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
let Inst{20} = 1;
}
-def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
+def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr!, $dsts",
@@ -97,7 +97,7 @@
let Inst{20} = 1;
}
-def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
+def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr!, $dsts",
@@ -107,19 +107,19 @@
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
-def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
+def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
variable_ops), IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
let Inst{20} = 0;
}
-def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
+def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
variable_ops), IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
let Inst{20} = 0;
}
-def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
+def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr!, $srcs",
@@ -127,7 +127,7 @@
let Inst{20} = 0;
}
-def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
+def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr!, $srcs",
Modified: llvm/branches/release_28/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_28/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=113540&r1=113539&r2=113540&view=diff
==============================================================================
--- llvm/branches/release_28/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/branches/release_28/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Sep 9 15:56:38 2010
@@ -315,6 +315,18 @@
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
if (!isARMLowRegister(BaseReg) || Mode != ARM_AM::ia)
return false;
+ // For the non-writeback version (this one), the base register must be
+ // one of the registers being loaded.
+ bool isOK = false;
+ for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
+ if (MI->getOperand(i).getReg() == BaseReg) {
+ isOK = true;
+ break;
+ }
+ }
+ if (!isOK)
+ return false;
+
OpNum = 0;
isLdStMul = true;
break;
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