[llvm-branch-commits] [llvm-branch] r119230 - in /llvm/branches/Apple/whitney: lib/Target/X86/X86InstrExtension.td test/MC/X86/x86-32-coverage.s utils/TableGen/AsmMatcherEmitter.cpp
Daniel Dunbar
daniel at zuster.org
Mon Nov 15 13:44:48 PST 2010
Author: ddunbar
Date: Mon Nov 15 15:44:48 2010
New Revision: 119230
URL: http://llvm.org/viewvc/llvm-project?rev=119230&view=rev
Log:
Merge r117897:
--
Author: Chris Lattner <clattner at apple.com>
Date: Mon Nov 1 04:44:29 2010 +0000
make the asm matcher emitter reject instructions that have comments
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
Modified:
llvm/branches/Apple/whitney/lib/Target/X86/X86InstrExtension.td
llvm/branches/Apple/whitney/test/MC/X86/x86-32-coverage.s
llvm/branches/Apple/whitney/utils/TableGen/AsmMatcherEmitter.cpp
Modified: llvm/branches/Apple/whitney/lib/Target/X86/X86InstrExtension.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/X86/X86InstrExtension.td?rev=119230&r1=119229&r2=119230&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/X86/X86InstrExtension.td (original)
+++ llvm/branches/Apple/whitney/lib/Target/X86/X86InstrExtension.td Mon Nov 15 15:44:48 2010
@@ -98,12 +98,12 @@
// instead of GR32. This allows them to operate on h registers on x86-64.
def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
(outs GR32_NOREX:$dst), (ins GR8:$src),
- "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
+ "movz{bl|x}\t{$src, $dst|$dst, $src}",
[]>, TB;
let mayLoad = 1 in
def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
(outs GR32_NOREX:$dst), (ins i8mem:$src),
- "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
+ "movz{bl|x}\t{$src, $dst|$dst, $src}",
[]>, TB;
// MOVSX64rr8 always has a REX prefix and it has an 8-bit register
Modified: llvm/branches/Apple/whitney/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/test/MC/X86/x86-32-coverage.s?rev=119230&r1=119229&r2=119230&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/branches/Apple/whitney/test/MC/X86/x86-32-coverage.s Mon Nov 15 15:44:48 2010
@@ -18,7 +18,7 @@
// CHECK: movswl 3735928559(%ebx,%ecx,8), %ecx
movswl 0xdeadbeef(%ebx,%ecx,8),%ecx
-// CHECK: movzbl 3735928559(%ebx,%ecx,8), %ecx # NOREX
+// CHECK: movzbl 3735928559(%ebx,%ecx,8), %ecx
movzbl 0xdeadbeef(%ebx,%ecx,8),%ecx
// CHECK: movzwl 3735928559(%ebx,%ecx,8), %ecx
@@ -11807,19 +11807,19 @@
// CHECK: movswl 305419896, %ecx
movswl 0x12345678,%ecx
-// CHECK: movzbl 3735928559(%ebx,%ecx,8), %ecx # NOREX
+// CHECK: movzbl 3735928559(%ebx,%ecx,8), %ecx
movzbl 0xdeadbeef(%ebx,%ecx,8),%ecx
-// CHECK: movzbl 69, %ecx # NOREX
+// CHECK: movzbl 69, %ecx
movzbl 0x45,%ecx
-// CHECK: movzbl 32493, %ecx # NOREX
+// CHECK: movzbl 32493, %ecx
movzbl 0x7eed,%ecx
-// CHECK: movzbl 3133065982, %ecx # NOREX
+// CHECK: movzbl 3133065982, %ecx
movzbl 0xbabecafe,%ecx
-// CHECK: movzbl 305419896, %ecx # NOREX
+// CHECK: movzbl 305419896, %ecx
movzbl 0x12345678,%ecx
// CHECK: movzbw 3735928559(%ebx,%ecx,8), %bx
Modified: llvm/branches/Apple/whitney/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/utils/TableGen/AsmMatcherEmitter.cpp?rev=119230&r1=119229&r2=119230&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/branches/Apple/whitney/utils/TableGen/AsmMatcherEmitter.cpp Mon Nov 15 15:44:48 2010
@@ -355,26 +355,18 @@
/// function.
std::string ConversionFnKind;
- InstructionInfo(const CodeGenInstruction &CGI, StringRef CommentDelimiter)
+ InstructionInfo(const CodeGenInstruction &CGI)
: TheDef(CGI.TheDef), OperandList(CGI.Operands) {
InstrName = TheDef->getName();
// TODO: Eventually support asmparser for Variant != 0.
AsmString = CGI.FlattenAsmStringVariants(CGI.AsmString, 0);
- // Remove comments from the asm string. We know that the asmstring only
- // has one line.
- if (!CommentDelimiter.empty()) {
- size_t Idx = StringRef(AsmString).find(CommentDelimiter);
- if (Idx != StringRef::npos)
- AsmString = AsmString.substr(0, Idx);
- }
-
TokenizeAsmString(AsmString, Tokens);
}
/// isAssemblerInstruction - Return true if this matchable is a valid thing to
/// match against.
- bool isAssemblerInstruction() const;
+ bool isAssemblerInstruction(StringRef CommentDelimiter) const;
/// getSingletonRegisterForToken - If the specified token is a singleton
/// register, return the Record for it, otherwise return null.
@@ -465,9 +457,6 @@
/// Target - The target information.
CodeGenTarget &Target;
- /// The AsmParser "CommentDelimiter" value.
- std::string CommentDelimiter;
-
/// The AsmParser "RegisterPrefix" value.
std::string RegisterPrefix;
@@ -567,7 +556,7 @@
return 0;
}
-bool InstructionInfo::isAssemblerInstruction() const {
+bool InstructionInfo::isAssemblerInstruction(StringRef CommentDelimiter) const {
StringRef Name = InstrName;
// Reject instructions with no .s string.
@@ -581,6 +570,14 @@
"multiline instruction is not valid for the asmparser, "
"mark it isCodeGenOnly");
+ // Remove comments from the asm string. We know that the asmstring only
+ // has one line.
+ if (!CommentDelimiter.empty() &&
+ StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
+ throw TGError(TheDef->getLoc(),
+ "asmstring for instruction has comment character in it, "
+ "mark it isCodeGenOnly");
+
// Reject instructions with attributes, these aren't something we can handle,
// the target should be refactored to use operands instead of modifiers.
//
@@ -674,10 +671,8 @@
if (OI.Rec->isSubClassOf("RegisterClass")) {
ClassInfo *CI = RegisterClassClasses[OI.Rec];
- if (!CI) {
- PrintError(OI.Rec->getLoc(), "register class has no class info!");
- throw std::string("ERROR: Missing register class!");
- }
+ if (!CI)
+ throw TGError(OI.Rec->getLoc(), "register class has no class info!");
return CI;
}
@@ -686,10 +681,8 @@
Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
ClassInfo *CI = AsmOperandClasses[MatchClass];
- if (!CI) {
- PrintError(OI.Rec->getLoc(), "operand has no match class!");
- throw std::string("ERROR: Missing match class!");
- }
+ if (!CI)
+ throw TGError(OI.Rec->getLoc(), "operand has no match class!");
return CI;
}
@@ -876,7 +869,6 @@
AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target)
: AsmParser(asmParser), Target(target),
- CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
{
}
@@ -891,16 +883,16 @@
if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
continue;
- if (Pred->getName().empty()) {
- PrintError(Pred->getLoc(), "Predicate has no name!");
- throw std::string("ERROR: Predicate defs must be named");
- }
+ if (Pred->getName().empty())
+ throw TGError(Pred->getLoc(), "Predicate has no name!");
unsigned FeatureNo = SubtargetFeatures.size();
SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo);
assert(FeatureNo < 32 && "Too many subtarget features!");
}
+ StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter");
+
// Parse the instructions; we need to do this first so that we can gather the
// singleton register classes.
SmallPtrSet<Record*, 16> SingletonRegisters;
@@ -917,11 +909,11 @@
if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
continue;
- OwningPtr<InstructionInfo> II(new InstructionInfo(CGI, CommentDelimiter));
+ OwningPtr<InstructionInfo> II(new InstructionInfo(CGI));
// Ignore instructions which shouldn't be matched and diagnose invalid
// instruction definitions with an error.
- if (!II->isAssemblerInstruction())
+ if (!II->isAssemblerInstruction(CommentDelimiter))
continue;
// Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
@@ -1010,8 +1002,8 @@
// Map this token to an operand. FIXME: Move elsewhere.
unsigned Idx;
if (!II->OperandList.hasOperandNamed(OperandName, Idx))
- throw std::string("error: unable to find operand: '" +
- OperandName.str() + "'");
+ throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" +
+ OperandName.str() + "'");
// FIXME: This is annoying, the named operand may be tied (e.g.,
// XCHG8rm). What we want is the untied operand, which we now have to
@@ -1536,8 +1528,7 @@
// We can't have two aliases from the same mnemonic with no predicate.
PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
"two MnemonicAliases with the same 'from' mnemonic!");
- PrintError(R->getLoc(), "this is the other MnemonicAlias.");
- throw std::string("ERROR: Invalid MnemonicAlias definitions!");
+ throw TGError(R->getLoc(), "this is the other MnemonicAlias.");
}
AliasWithNoPredicate = i;
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