[llvm-branch-commits] [llvm-branch] r105093 - in /llvm/branches/Apple/Morbo: lib/Target/ARM/ARMInstrFormats.td lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/sibcall-3.ll

[Evan Cheng]

Author: evancheng
Date: Fri May 28 20:48:44 2010
New Revision: 105093

URL: http://llvm.org/viewvc/llvm-project?rev=105093&view=rev
Log:
Merge 105092.

Added:
    llvm/branches/Apple/Morbo/test/CodeGen/X86/sibcall-3.ll
      - copied unchanged from r105092, llvm/trunk/test/CodeGen/X86/sibcall-3.ll
Modified:
    llvm/branches/Apple/Morbo/lib/Target/ARM/ARMInstrFormats.td   (props changed)
    llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp

Propchange: llvm/branches/Apple/Morbo/lib/Target/ARM/ARMInstrFormats.td
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri May 28 20:48:44 2010
@@ -1,2 +1,2 @@
 /llvm/branches/Apple/Hermes/lib/Target/ARM/ARMInstrFormats.td:104930
-/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td:98980,104182,104233,104236,104265,104274,104302,104338,104412,104419,104524,104531,104640,104646,104649,104655-104656,104661,104664,104705-104706,104720,104722,104732,104737,104740,104785,104848,104900
+/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td:98980,104182,104233,104236,104265,104274,104302,104338,104412,104419,104524,104531,104640,104646,104649,104655-104656,104661,104664,104705-104706,104720,104722,104732,104737,104740,104785,104848,104900,105092

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp?rev=105093&r1=105092&r2=105093&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp Fri May 28 20:48:44 2010
@@ -2445,6 +2445,24 @@
         }
       }
     }
+
+    // If the tailcall address may be in a register, then make sure it's
+    // possible to register allocate for it. In 32-bit, the call address can
+    // only target EAX, EDX, or ECX since the tail call must be scheduled after
+    // callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI,
+    // RDI, R8, R9, R11.
+    if (!isa<GlobalAddressSDNode>(Callee) &&
+        !isa<ExternalSymbolSDNode>(Callee)) {
+      unsigned Limit = Subtarget->is64Bit() ? 8 : 3;
+      unsigned NumInRegs = 0;
+      for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+        CCValAssign &VA = ArgLocs[i];
+        if (VA.isRegLoc()) {
+          if (++NumInRegs == Limit)
+            return false;
+        }
+      }
+    }
   }
 
   return true;