[llvm-branch-commits] [llvm-branch] r104349 - in /llvm/branches/Apple/whitney/lib/Target/PowerPC: PPCISelDAGToDAG.cpp PPCISelLowering.h PPCInstrInfo.cpp PPCInstrInfo.td PPCRegisterInfo.cpp
Daniel Dunbar
daniel at zuster.org
Fri May 21 12:06:26 PDT 2010
Author: ddunbar
Date: Fri May 21 14:06:26 2010
New Revision: 104349
URL: http://llvm.org/viewvc/llvm-project?rev=104349&view=rev
Log:
The PPC MFCR instruction implicitly uses all 8 of the CR registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628.
Modified:
llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelLowering.h
llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.td
llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified: llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=104349&r1=104348&r2=104349&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri May 21 14:06:26 2010
@@ -712,8 +712,9 @@
if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
CCReg), 0);
- else
- IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
+ else
+ IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
+ CR7Reg, CCReg), 0);
SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
getI32Imm(31), getI32Imm(31) };
@@ -848,7 +849,8 @@
return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
N->getOperand(0), InFlag);
else
- return CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, InFlag);
+ return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
+ N->getOperand(0), InFlag);
}
case ISD::SDIV: {
Modified: llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelLowering.h?rev=104349&r1=104348&r2=104349&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCISelLowering.h Fri May 21 14:06:26 2010
@@ -111,9 +111,10 @@
/// Return with a flag operand, matched by 'blr'
RET_FLAG,
- /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
- /// This copies the bits corresponding to the specified CRREG into the
- /// resultant GPR. Bits corresponding to other CR regs are undefined.
+ /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
+ /// instructions. This copies the bits corresponding to the specified
+ /// CRREG into the resultant GPR. Bits corresponding to other CR regs
+ /// are undefined.
MFCR,
/// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
Modified: llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=104349&r1=104348&r2=104349&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.cpp Fri May 21 14:06:26 2010
@@ -442,7 +442,8 @@
// issue a MFCR to save all of the CRBits.
unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
PPC::R2 : PPC::R0;
- NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg));
+ NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
+ .addReg(SrcReg, getKillRegState(isKill)));
// If the saved register wasn't CR0, shift the bits left so that they are
// in CR0's slot.
Modified: llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.td?rev=104349&r1=104348&r2=104349&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCInstrInfo.td Fri May 21 14:06:26 2010
@@ -1117,14 +1117,17 @@
def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
"mtcrf $FXM, $rS", BrMCRX>,
PPC970_MicroCode, PPC970_Unit_CRU;
-// FIXME: this Uses all the CR registers. Marking it as such is
-// necessary for DeadMachineInstructionElim to do the right thing.
-// However, marking it also exposes PR 2964, and causes crashes in
-// the Local RA because it doesn't like this sequence:
+
+// This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
+// declaring that here gives the local register allocator problems with this:
// vreg = MCRF CR0
// MFCR <kill of whatever preg got assigned to vreg>
-// For now DeadMachineInstructionElim is turned off, so don't do the marking.
-def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
+// while not declaring it breaks DeadMachineInstructionElimination.
+// As it turns out, in all cases where we currently use this,
+// we're only interested in one subregister of it. Represent this in the
+// instruction to keep the register allocator from becoming confused.
+def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
+ "mfcr $rT ${:comment} $FXM", SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
"mfcr $rT, $FXM", SprMFCR>,
Modified: llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=104349&r1=104348&r2=104349&view=diff
==============================================================================
--- llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/Apple/whitney/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri May 21 14:06:26 2010
@@ -689,19 +689,15 @@
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
+ unsigned SrcReg = MI.getOperand(0).getReg();
// We need to store the CR in the low 4-bits of the saved value. First, issue
- // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
- if (!MI.getOperand(0).isKill())
- BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
- else
- // Implicitly kill the CR register.
- BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
- .addReg(MI.getOperand(0).getReg(), RegState::ImplicitKill);
+ // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
+ BuildMI(MBB, II, dl, TII.get(PPC::MFCRpseud), Reg)
+ .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
// If the saved register wasn't CR0, shift the bits left so that they are in
// CR0's slot.
- unsigned SrcReg = MI.getOperand(0).getReg();
if (SrcReg != PPC::CR0)
// rlwinm rA, rA, ShiftBits, 0, 31.
BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
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