[llvm-branch-commits] [llvm-branch] r104065 - in /llvm/branches/Apple/Morbo: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2010-05-18-PostIndexBug.ll

[Evan Cheng]

Author: evancheng
Date: Tue May 18 16:44:32 2010
New Revision: 104065

URL: http://llvm.org/viewvc/llvm-project?rev=104065&view=rev
Log:
Merge 104060.

Added:
    llvm/branches/Apple/Morbo/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
      - copied, changed from r104060, llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
Modified:
    llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=104065&r1=104064&r2=104065&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 18 16:44:32 2010
@@ -5258,10 +5258,6 @@
     SDValue Offset;
     ISD::MemIndexedMode AM = ISD::UNINDEXED;
     if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
-      if (Ptr == Offset && Op->getOpcode() == ISD::ADD)
-        std::swap(BasePtr, Offset);
-      if (Ptr != BasePtr)
-        continue;
       // Don't create a indexed load / store with zero offset.
       if (isa<ConstantSDNode>(Offset) &&
           cast<ConstantSDNode>(Offset)->isNullValue())

Modified: llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp?rev=104065&r1=104064&r2=104065&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/ARM/ARMISelLowering.cpp Tue May 18 16:44:32 2010
@@ -4436,9 +4436,11 @@
   bool isSEXTLoad = false;
   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
     VT  = LD->getMemoryVT();
+    Ptr = LD->getBasePtr();
     isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
   } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
     VT  = ST->getMemoryVT();
+    Ptr = ST->getBasePtr();
   } else
     return false;
 
@@ -4446,13 +4448,25 @@
   bool isLegal = false;
   if (Subtarget->isThumb2())
     isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
-                                        isInc, DAG);
+                                       isInc, DAG);
   else
     isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
                                         isInc, DAG);
   if (!isLegal)
     return false;
 
+  if (Ptr != Base) {
+    // Swap base ptr and offset to catch more post-index load / store when
+    // it's legal. In Thumb2 mode, offset must be an immediate.
+    if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
+        !Subtarget->isThumb2())
+      std::swap(Base, Offset);
+
+    // Post-indexed load / store update the base pointer.
+    if (Ptr != Base)
+      return false;
+  }
+
   AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
   return true;
 }

Copied: llvm/branches/Apple/Morbo/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll (from r104060, llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll?p2=llvm/branches/Apple/Morbo/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll&p1=llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll&r1=104060&r2=104065&rev=104065&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll Tue May 18 16:44:32 2010
@@ -7,10 +7,10 @@
 define arm_apcscc zeroext i8 @t(%struct.foo* %this) noreturn optsize {
 entry:
 ; ARM:       t:
-; ARM:       str r0, [r1], r0
+; ARM:       str r0, [r1], +r0
 
 ; THUMB:     t:
-; THUMB-NOT: str r0, [r1], r0
+; THUMB-NOT: str r0, [r1], +r0
 ; THUMB:     str r0, [r1]
   %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
   store i32 undef, i32* inttoptr (i32 8 to i32*), align 8