[llvm-branch-commits] [llvm-branch] r103955 - in /llvm/branches/Apple/Morbo: lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ test/CodeGen/X86/
Evan Cheng
evan.cheng at apple.com
Mon May 17 11:27:29 PDT 2010
Author: evancheng
Date: Mon May 17 13:27:29 2010
New Revision: 103955
URL: http://llvm.org/viewvc/llvm-project?rev=103955&view=rev
Log:
Merge: 102455, 102456, 102467, 102487, 102488, 102492, 102493.
Added:
llvm/branches/Apple/Morbo/test/CodeGen/X86/promote-i16.ll
- copied unchanged from r102493, llvm/trunk/test/CodeGen/X86/promote-i16.ll
Modified:
llvm/branches/Apple/Morbo/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86Instr64bit.td
llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td
llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp
llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h
llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-07-11-SpillerBug.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-08-05-SpillerBug.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/atomic_add.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/h-registers-0.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/ins_subreg_coalesce-1.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/rot16.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/rot32.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/shl_elim.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/store-narrow.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/tls11.ll
llvm/branches/Apple/Morbo/test/CodeGen/X86/xor.ll
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Mon May 17 13:27:29 2010
@@ -470,10 +470,11 @@
for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
II != IE; ++II) {
// Print the assembly for the instruction.
- if (!II->isLabel() && !II->isDebugValue())
+ if (!II->isLabel() && !II->isImplicitDef() && !II->isKill() &&
+ !II->isDebugValue()) {
HasAnyRealCode = true;
-
- ++EmittedInsts;
+ ++EmittedInsts;
+ }
// FIXME: Clean up processDebugLoc.
processDebugLoc(II, true);
Modified: llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 17 13:27:29 2010
@@ -656,19 +656,22 @@
&DeadNodes);
removeFromWorkList(Load);
DAG.DeleteNode(Load);
+ AddToWorkList(Trunc.getNode());
}
SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
Replace = false;
DebugLoc dl = Op.getDebugLoc();
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
- ISD::LoadExtType ExtType =
- ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD : LD->getExtensionType();
+ EVT MemVT = LD->getMemoryVT();
+ ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
+ ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
+ : LD->getExtensionType();
Replace = true;
return DAG.getExtLoad(ExtType, dl, PVT,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
- LD->getMemoryVT(), LD->isVolatile(),
+ MemVT, LD->isVolatile(),
LD->isNonTemporal(), LD->getAlignment());
}
@@ -704,6 +707,7 @@
SDValue NewOp = PromoteOperand(Op, PVT, Replace);
if (NewOp.getNode() == 0)
return SDValue();
+ AddToWorkList(NewOp.getNode());
if (Replace)
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
@@ -718,6 +722,7 @@
SDValue NewOp = PromoteOperand(Op, PVT, Replace);
if (NewOp.getNode() == 0)
return SDValue();
+ AddToWorkList(NewOp.getNode());
if (Replace)
ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
@@ -767,6 +772,8 @@
if (Replace1)
ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
+ DEBUG(dbgs() << "\nPromoting ";
+ Op.getNode()->dump(&DAG));
DebugLoc dl = Op.getDebugLoc();
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(Opc, dl, PVT, NN0, NN1));
@@ -812,6 +819,8 @@
if (Replace)
ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
+ DEBUG(dbgs() << "\nPromoting ";
+ Op.getNode()->dump(&DAG));
DebugLoc dl = Op.getDebugLoc();
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
@@ -841,6 +850,8 @@
// fold (aext (aext x)) -> (aext x)
// fold (aext (zext x)) -> (zext x)
// fold (aext (sext x)) -> (sext x)
+ DEBUG(dbgs() << "\nPromoting ";
+ Op.getNode()->dump(&DAG));
return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
}
return SDValue();
@@ -869,12 +880,14 @@
DebugLoc dl = Op.getDebugLoc();
SDNode *N = Op.getNode();
LoadSDNode *LD = cast<LoadSDNode>(N);
- ISD::LoadExtType ExtType =
- ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD : LD->getExtensionType();
+ EVT MemVT = LD->getMemoryVT();
+ ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
+ ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
+ : LD->getExtensionType();
SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(),
- LD->getMemoryVT(), LD->isVolatile(),
+ MemVT, LD->isVolatile(),
LD->isNonTemporal(), LD->getAlignment());
SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
@@ -888,6 +901,7 @@
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
removeFromWorkList(N);
DAG.DeleteNode(N);
+ AddToWorkList(Result.getNode());
return true;
}
return false;
@@ -997,7 +1011,7 @@
}
SDValue DAGCombiner::visit(SDNode *N) {
- switch(N->getOpcode()) {
+ switch (N->getOpcode()) {
default: break;
case ISD::TokenFactor: return visitTokenFactor(N);
case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
@@ -1082,6 +1096,35 @@
}
}
+ // If nothing happened still, try promoting the operation.
+ if (RV.getNode() == 0) {
+ switch (N->getOpcode()) {
+ default: break;
+ case ISD::ADD:
+ case ISD::SUB:
+ case ISD::MUL:
+ case ISD::AND:
+ case ISD::OR:
+ case ISD::XOR:
+ RV = PromoteIntBinOp(SDValue(N, 0));
+ break;
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
+ RV = PromoteIntShiftOp(SDValue(N, 0));
+ break;
+ case ISD::SIGN_EXTEND:
+ case ISD::ZERO_EXTEND:
+ case ISD::ANY_EXTEND:
+ RV = PromoteExtend(SDValue(N, 0));
+ break;
+ case ISD::LOAD:
+ if (PromoteLoad(SDValue(N, 0)))
+ RV = SDValue(N, 0);
+ break;
+ }
+ }
+
// If N is a commutative binary node, try commuting it to enable more
// sdisel CSE.
if (RV.getNode() == 0 &&
@@ -1373,7 +1416,7 @@
N0.getOperand(0).getOperand(1),
N0.getOperand(1)));
- return PromoteIntBinOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitADDC(SDNode *N) {
@@ -1511,7 +1554,7 @@
VT);
}
- return PromoteIntBinOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitMUL(SDNode *N) {
@@ -1604,7 +1647,7 @@
if (RMUL.getNode() != 0)
return RMUL;
- return PromoteIntBinOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitSDIV(SDNode *N) {
@@ -2250,7 +2293,7 @@
}
}
- return PromoteIntBinOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitOR(SDNode *N) {
@@ -2376,7 +2419,7 @@
if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
return SDValue(Rot, 0);
- return PromoteIntBinOp(SDValue(N, 0));
+ return SDValue();
}
/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
@@ -2685,7 +2728,7 @@
SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
- return PromoteIntBinOp(SDValue(N, 0));
+ return SDValue();
}
/// visitShiftByConstant - Handle transforms common to the three shifts, when
@@ -2852,7 +2895,7 @@
return NewSHL;
}
- return PromoteIntShiftOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitSRA(SDNode *N) {
@@ -2972,7 +3015,7 @@
return NewSRA;
}
- return PromoteIntShiftOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitSRL(SDNode *N) {
@@ -3129,7 +3172,7 @@
}
}
- return PromoteIntShiftOp(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitCTLZ(SDNode *N) {
@@ -3526,7 +3569,7 @@
DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
- return PromoteExtend(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
@@ -3689,7 +3732,7 @@
N0.getOperand(1)));
}
- return PromoteExtend(SDValue(N, 0));
+ return SDValue();
}
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
@@ -3825,7 +3868,7 @@
return SCC;
}
- return PromoteExtend(SDValue(N, 0));
+ return SDValue();
}
/// GetDemandedBits - See if the specified operand can be simplified with the
@@ -5426,8 +5469,6 @@
if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
return SDValue(N, 0);
- if (PromoteLoad(SDValue(N, 0)))
- return SDValue(N, 0);
return SDValue();
}
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelDAGToDAG.cpp Mon May 17 13:27:29 2010
@@ -1841,6 +1841,9 @@
// Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
// use a smaller encoding.
+ if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse())
+ // Look past the truncate if CMP is the only use of it.
+ N0 = N0.getOperand(0);
if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
N0.getValueType() != MVT::i8 &&
X86::isZeroNode(N1)) {
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp Mon May 17 13:27:29 2010
@@ -6102,7 +6102,7 @@
// the encoding for the i16 version is larger than the i32 version.
// Also promote i16 to i32 for performance / code size reason.
if (LHS.getValueType() == MVT::i8 ||
- (Subtarget->shouldPromote16Bit() && LHS.getValueType() == MVT::i16))
+ LHS.getValueType() == MVT::i16)
LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
// If the operand types disagree, extend the shift amount to match. Since
@@ -9610,9 +9610,13 @@
}
static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) {
+ if (DCI.isBeforeLegalizeOps())
+ return SDValue();
+
EVT VT = N->getValueType(0);
- if (VT != MVT::i64 || !Subtarget->is64Bit())
+ if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
return SDValue();
// fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
@@ -9622,6 +9626,8 @@
std::swap(N0, N1);
if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
return SDValue();
+ if (!N0.hasOneUse() || !N1.hasOneUse())
+ return SDValue();
SDValue ShAmt0 = N0.getOperand(1);
if (ShAmt0.getValueType() != MVT::i8)
@@ -9644,10 +9650,11 @@
std::swap(ShAmt0, ShAmt1);
}
+ unsigned Bits = VT.getSizeInBits();
if (ShAmt1.getOpcode() == ISD::SUB) {
SDValue Sum = ShAmt1.getOperand(0);
if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
- if (SumC->getSExtValue() == 64 &&
+ if (SumC->getSExtValue() == Bits &&
ShAmt1.getOperand(1) == ShAmt0)
return DAG.getNode(Opc, DL, VT,
Op0, Op1,
@@ -9657,7 +9664,7 @@
} else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
if (ShAmt0C &&
- ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == 64)
+ ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
return DAG.getNode(Opc, DL, VT,
N0.getOperand(0), N1.getOperand(0),
DAG.getNode(ISD::TRUNCATE, DL,
@@ -9936,7 +9943,7 @@
case ISD::SHL:
case ISD::SRA:
case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
- case ISD::OR: return PerformOrCombine(N, DAG, Subtarget);
+ case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
case X86ISD::FXOR:
case X86ISD::FOR: return PerformFORCombine(N, DAG);
@@ -9957,7 +9964,7 @@
bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
if (!isTypeLegal(VT))
return false;
- if (!Subtarget->shouldPromote16Bit() || VT != MVT::i16)
+ if (VT != MVT::i16)
return true;
switch (Opc) {
@@ -9968,7 +9975,6 @@
case ISD::ZERO_EXTEND:
case ISD::ANY_EXTEND:
case ISD::SHL:
- case ISD::SRA:
case ISD::SRL:
case ISD::SUB:
case ISD::ADD:
@@ -9992,9 +9998,6 @@
/// beneficial for dag combiner to promote the specified node. If true, it
/// should return the desired promotion type by reference.
bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
- if (!Subtarget->shouldPromote16Bit())
- return false;
-
EVT VT = Op.getValueType();
if (VT != MVT::i16)
return false;
@@ -10007,10 +10010,16 @@
LoadSDNode *LD = cast<LoadSDNode>(Op);
// If the non-extending load has a single use and it's not live out, then it
// might be folded.
- if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
- Op.hasOneUse() &&
- Op.getNode()->use_begin()->getOpcode() != ISD::CopyToReg)
- return false;
+ if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
+ Op.hasOneUse()*/) {
+ for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
+ UE = Op.getNode()->use_end(); UI != UE; ++UI) {
+ // The only case where we'd want to promote LOAD (rather then it being
+ // promoted as an operand is when it's only use is liveout.
+ if (UI->getOpcode() != ISD::CopyToReg)
+ return false;
+ }
+ }
Promote = true;
break;
}
@@ -10020,7 +10029,6 @@
Promote = true;
break;
case ISD::SHL:
- case ISD::SRA:
case ISD::SRL: {
SDValue N0 = Op.getOperand(0);
// Look out for (store (shl (load), x)).
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86Instr64bit.td?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86Instr64bit.td Mon May 17 13:27:29 2010
@@ -2094,6 +2094,11 @@
(EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
+def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
+ (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
+ GR32_ABCD)),
+ x86_subreg_8bit_hi))>,
+ Requires<[In64BitMode]>;
def : Pat<(srl GR16:$src, (i8 8)),
(EXTRACT_SUBREG
(MOVZX32_NOREXrr8
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrInfo.td Mon May 17 13:27:29 2010
@@ -329,8 +329,6 @@
def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
def HasAES : Predicate<"Subtarget->hasAES()">;
-def Promote16Bit : Predicate<"Subtarget->shouldPromote16Bit()">;
-def NotPromote16Bit : Predicate<"!Subtarget->shouldPromote16Bit()">;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.
@@ -4499,12 +4497,10 @@
// avoid partial-register updates.
def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
-def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>,
- Requires<[NotPromote16Bit]>;
+// Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
def : Pat<(i32 (anyext GR16:$src)),
- (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>,
- Requires<[Promote16Bit]>;
+ (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
//===----------------------------------------------------------------------===//
@@ -4566,11 +4562,11 @@
// h-register tricks
def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
- (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
+ (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
x86_subreg_8bit_hi)>,
Requires<[In32BitMode]>;
def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
- (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
+ (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
x86_subreg_8bit_hi)>,
Requires<[In32BitMode]>;
def : Pat<(srl GR16:$src, (i8 8)),
@@ -4595,6 +4591,11 @@
GR32_ABCD)),
x86_subreg_8bit_hi))>,
Requires<[In32BitMode]>;
+def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
+ (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
+ GR32_ABCD)),
+ x86_subreg_8bit_hi))>,
+ Requires<[In32BitMode]>;
// (shl x, 1) ==> (add x, x)
def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.cpp Mon May 17 13:27:29 2010
@@ -16,7 +16,6 @@
#include "X86InstrInfo.h"
#include "X86GenSubtarget.inc"
#include "llvm/GlobalValue.h"
-#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/System/Host.h"
@@ -25,10 +24,6 @@
#include "llvm/ADT/SmallVector.h"
using namespace llvm;
-static cl::opt<bool>
-DoPromote16Bit("promote-16bit", cl::Hidden,
- cl::desc("Promote 16-bit instructions"));
-
#if defined(_MSC_VER)
#include <intrin.h>
#endif
@@ -298,7 +293,6 @@
, IsBTMemSlow(false)
, IsUAMemFast(false)
, HasVectorUAMem(false)
- , Promote16Bit(DoPromote16Bit)
, DarwinVers(0)
, stackAlignment(8)
// FIXME: this is a known good value for Yonah. How about others?
Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86Subtarget.h Mon May 17 13:27:29 2010
@@ -88,10 +88,6 @@
/// operands. This may require setting a feature bit in the processor.
bool HasVectorUAMem;
- /// Promote16Bit - True if codegen should promote 16-bit operations to 32-bit.
- /// This is a temporary option.
- bool Promote16Bit;
-
/// DarwinVers - Nonzero if this is a darwin platform: the numeric
/// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
unsigned char DarwinVers; // Is any darwin-x86 platform.
@@ -160,7 +156,6 @@
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }
- bool shouldPromote16Bit() const { return Promote16Bit; }
bool isTargetDarwin() const { return TargetType == isDarwin; }
bool isTargetELF() const { return TargetType == isELF; }
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-07-11-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-07-11-SpillerBug.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-07-11-SpillerBug.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-07-11-SpillerBug.ll Mon May 17 13:27:29 2010
@@ -3,6 +3,7 @@
; CHECK: andl $65534, %
; CHECK-NEXT: movl %
+; CHECK-NEXT: movzwl
; CHECK-NEXT: movl $17
@g_5 = external global i16 ; <i16*> [#uses=2]
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-08-05-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-08-05-SpillerBug.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-08-05-SpillerBug.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-08-05-SpillerBug.ll Mon May 17 13:27:29 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -disable-fp-elim -stats |& grep asm-printer | grep 56
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -disable-fp-elim -stats |& grep asm-printer | grep 55
; PR2568
@g_3 = external global i16 ; <i16*> [#uses=1]
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/2008-10-16-SpillerBug.ll Mon May 17 13:27:29 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 40
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 41
; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s
%struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
@@ -63,13 +63,13 @@
define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind {
entry:
; CHECK: t:
-; CHECK: xorl %ecx, %ecx
%0 = trunc i64 %key_token to i32 ; <i32> [#uses=1]
%1 = getelementptr %struct.YYToken* %pstrm, i32 %0 ; <%struct.YYToken*> [#uses=5]
br label %bb1132
bb51: ; preds = %bb1132
; CHECK: .align 4
+; CHECK: xorl %ecx, %ecx
; CHECK: andl $7
%2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0 ; <i16*> [#uses=1]
%3 = load i16* %2, align 1 ; <i16> [#uses=3]
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Mon May 17 13:27:29 2010
@@ -4,7 +4,7 @@
; rdar://6808032
; CHECK: pextrw $14
-; CHECK-NEXT: movzbl
+; CHECK-NEXT: shrl $8
; CHECK-NEXT: (%ebp)
; CHECK-NEXT: pinsrw
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/atomic_add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/atomic_add.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/atomic_add.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/atomic_add.ll Mon May 17 13:27:29 2010
@@ -192,7 +192,7 @@
define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
entry:
; CHECK: sub2:
-; CHECK: subw
+; CHECK: negl
%0 = trunc i32 %v to i16 ; <i16> [#uses=1]
%1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0]
ret void
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll Mon May 17 13:27:29 2010
@@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \
-; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 10
+; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 9
; RUN: grep {leal 1(\%rsi),} %t
define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize {
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/h-registers-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/h-registers-0.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/h-registers-0.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/h-registers-0.ll Mon May 17 13:27:29 2010
@@ -1,12 +1,16 @@
-; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4
-; RUN: llc < %s -march=x86 > %t
-; RUN: grep {incb %ah} %t | count 3
-; RUN: grep {movzbl %ah,} %t | count 3
+; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64
+; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32
; Use h registers. On x86-64, codegen doesn't support general allocation
; of h registers yet, due to x86 encoding complications.
define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
+; X86-64: bar64:
+; X86-64: shrq $8, %rdi
+; X86-64: incb %dil
+
+; X86-32: bar64:
+; X86-32: incb %ah
%t0 = lshr i64 %x, 8
%t1 = trunc i64 %t0 to i8
%t2 = add i8 %t1, 1
@@ -15,6 +19,12 @@
}
define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
+; X86-64: bar32:
+; X86-64: shrl $8, %edi
+; X86-64: incb %dil
+
+; X86-32: bar32:
+; X86-32: incb %ah
%t0 = lshr i32 %x, 8
%t1 = trunc i32 %t0 to i8
%t2 = add i8 %t1, 1
@@ -23,6 +33,12 @@
}
define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
+; X86-64: bar16:
+; X86-64: shrl $8, %edi
+; X86-64: incb %dil
+
+; X86-32: bar16:
+; X86-32: incb %ah
%t0 = lshr i16 %x, 8
%t1 = trunc i16 %t0 to i8
%t2 = add i8 %t1, 1
@@ -31,18 +47,36 @@
}
define i64 @qux64(i64 inreg %x) nounwind {
+; X86-64: qux64:
+; X86-64: movq %rdi, %rax
+; X86-64: movzbl %ah, %eax
+
+; X86-32: qux64:
+; X86-32: movzbl %ah, %eax
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
ret i64 %t1
}
define i32 @qux32(i32 inreg %x) nounwind {
+; X86-64: qux32:
+; X86-64: movl %edi, %eax
+; X86-64: movzbl %ah, %eax
+
+; X86-32: qux32:
+; X86-32: movzbl %ah, %eax
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
ret i32 %t1
}
define i16 @qux16(i16 inreg %x) nounwind {
+; X86-64: qux16:
+; X86-64: movl %edi, %eax
+; X86-64: movzbl %ah, %eax
+
+; X86-32: qux16:
+; X86-32: movzbl %ah, %eax
%t0 = lshr i16 %x, 8
ret i16 %t0
}
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/ins_subreg_coalesce-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/ins_subreg_coalesce-1.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/ins_subreg_coalesce-1.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/ins_subreg_coalesce-1.ll Mon May 17 13:27:29 2010
@@ -1,7 +1,13 @@
-; RUN: llc < %s -march=x86 | grep mov | count 3
+; RUN: llc < %s -march=x86 | FileCheck %s
-define fastcc i32 @sqlite3ExprResolveNames() nounwind {
+define fastcc i32 @t() nounwind {
entry:
+; CHECK: t:
+; CHECK: movzwl 0, %eax
+; CHECK: orl $2, %eax
+; CHECK: movw %ax, 0
+; CHECK: shrl $3, %eax
+; CHECK: andl $1, %eax
br i1 false, label %UnifiedReturnBlock, label %bb4
bb4: ; preds = %entry
br i1 false, label %bb17, label %bb22
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/rot16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/rot16.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/rot16.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/rot16.ll Mon May 17 13:27:29 2010
@@ -1,11 +1,9 @@
-; RUN: llc < %s -march=x86 > %t
-; RUN: grep rol %t | count 3
-; RUN: grep ror %t | count 1
-; RUN: grep shld %t | count 2
-; RUN: grep shrd %t | count 2
+; RUN: llc < %s -march=x86 | FileCheck %s
define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: foo:
+; CHECK: rolw %cl
%0 = shl i16 %x, %z
%1 = sub i16 16, %z
%2 = lshr i16 %x, %1
@@ -15,6 +13,8 @@
define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: bar:
+; CHECK: shldw %cl
%0 = shl i16 %y, %z
%1 = sub i16 16, %z
%2 = lshr i16 %x, %1
@@ -24,6 +24,8 @@
define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: un:
+; CHECK: rorw %cl
%0 = lshr i16 %x, %z
%1 = sub i16 16, %z
%2 = shl i16 %x, %1
@@ -33,6 +35,8 @@
define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: bu:
+; CHECK: shrdw
%0 = lshr i16 %y, %z
%1 = sub i16 16, %z
%2 = shl i16 %x, %1
@@ -42,6 +46,8 @@
define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: xfoo:
+; CHECK: rolw $5
%0 = lshr i16 %x, 11
%1 = shl i16 %x, 5
%2 = or i16 %0, %1
@@ -50,6 +56,8 @@
define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: xbar:
+; CHECK: shldw $5
%0 = shl i16 %y, 5
%1 = lshr i16 %x, 11
%2 = or i16 %0, %1
@@ -58,6 +66,8 @@
define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: xun:
+; CHECK: rolw $11
%0 = lshr i16 %x, 5
%1 = shl i16 %x, 11
%2 = or i16 %0, %1
@@ -66,6 +76,8 @@
define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
+; CHECK: xbu:
+; CHECK: shldw $11
%0 = lshr i16 %y, 5
%1 = shl i16 %x, 11
%2 = or i16 %0, %1
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/rot32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/rot32.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/rot32.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/rot32.ll Mon May 17 13:27:29 2010
@@ -1,11 +1,9 @@
-; RUN: llc < %s -march=x86 > %t
-; RUN: grep rol %t | count 3
-; RUN: grep ror %t | count 1
-; RUN: grep shld %t | count 2
-; RUN: grep shrd %t | count 2
+; RUN: llc < %s -march=x86 | FileCheck %s
define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: foo:
+; CHECK: roll %cl
%0 = shl i32 %x, %z
%1 = sub i32 32, %z
%2 = lshr i32 %x, %1
@@ -15,6 +13,8 @@
define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: bar:
+; CHECK: shldl %cl
%0 = shl i32 %y, %z
%1 = sub i32 32, %z
%2 = lshr i32 %x, %1
@@ -24,6 +24,8 @@
define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: un:
+; CHECK: rorl %cl
%0 = lshr i32 %x, %z
%1 = sub i32 32, %z
%2 = shl i32 %x, %1
@@ -33,6 +35,8 @@
define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: bu:
+; CHECK: shrdl %cl
%0 = lshr i32 %y, %z
%1 = sub i32 32, %z
%2 = shl i32 %x, %1
@@ -42,6 +46,8 @@
define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: xfoo:
+; CHECK: roll $7
%0 = lshr i32 %x, 25
%1 = shl i32 %x, 7
%2 = or i32 %0, %1
@@ -50,6 +56,8 @@
define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: xbar:
+; CHECK: shldl $7
%0 = shl i32 %y, 7
%1 = lshr i32 %x, 25
%2 = or i32 %0, %1
@@ -58,6 +66,8 @@
define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: xun:
+; CHECK: roll $25
%0 = lshr i32 %x, 7
%1 = shl i32 %x, 25
%2 = or i32 %0, %1
@@ -66,6 +76,8 @@
define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
+; CHECK: xbu:
+; CHECK: shldl
%0 = lshr i32 %y, 7
%1 = shl i32 %x, 25
%2 = or i32 %0, %1
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/shl_elim.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/shl_elim.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/shl_elim.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/shl_elim.ll Mon May 17 13:27:29 2010
@@ -2,7 +2,7 @@
; RUN: llc < %s -march=x86 | grep {shrl .eax}
; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
-define i32 @test1(i64 %a) {
+define i32 @test1(i64 %a) nounwind {
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
%tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1]
%tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1]
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/store-narrow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/store-narrow.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/store-narrow.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/store-narrow.ll Mon May 17 13:27:29 2010
@@ -50,8 +50,12 @@
%D = or i32 %B, %CS
store i32 %D, i32* %a0, align 4
ret void
-; CHECK: test4:
-; CHECK: movw %si, 2(%rdi)
+; X64: test4:
+; X64: movw %si, 2(%rdi)
+
+; X32: test4:
+; X32: movzwl 8(%esp), %eax
+; X32: movw %ax, 2(%{{.*}})
}
define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
@@ -63,8 +67,12 @@
%D = or i64 %B, %CS
store i64 %D, i64* %a0, align 4
ret void
-; CHECK: test5:
-; CHECK: movw %si, 2(%rdi)
+; X64: test5:
+; X64: movw %si, 2(%rdi)
+
+; X32: test5:
+; X32: movzwl 8(%esp), %eax
+; X32: movw %ax, 2(%{{.*}})
}
define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/tls11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/tls11.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/tls11.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/tls11.ll Mon May 17 13:27:29 2010
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t
-; RUN: grep {movw %gs:i at NTPOFF, %ax} %t
+; RUN: grep {movzwl %gs:i at NTPOFF, %eax} %t
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2
-; RUN: grep {movw %fs:i at TPOFF, %ax} %t2
+; RUN: grep {movzwl %fs:i at TPOFF, %eax} %t2
@i = thread_local global i16 15
Modified: llvm/branches/Apple/Morbo/test/CodeGen/X86/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/test/CodeGen/X86/xor.ll?rev=103955&r1=103954&r2=103955&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/test/CodeGen/X86/xor.ll (original)
+++ llvm/branches/Apple/Morbo/test/CodeGen/X86/xor.ll Mon May 17 13:27:29 2010
@@ -80,11 +80,11 @@
bb12:
ret i16 %tmp3
; X64: test5:
-; X64: notw [[REG:%[a-z]+]]
-; X64: andw {{.*}}[[REG]]
+; X64: notl [[REG:%[a-z]+]]
+; X64: andl {{.*}}[[REG]]
; X32: test5:
-; X32: notw [[REG:%[a-z]+]]
-; X32: andw {{.*}}[[REG]]
+; X32: notl [[REG:%[a-z]+]]
+; X32: andl {{.*}}[[REG]]
}
define i8 @test6(i8 %a, i8 %b) nounwind {
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