[llvm-branch-commits] [llvm-branch] r99290 - in /llvm/branches/release_27: ./ lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h

[Tanya Lattner]

Author: tbrethou
Date: Tue Mar 23 12:06:56 2010
New Revision: 99290

URL: http://llvm.org/viewvc/llvm-project?rev=99290&view=rev
Log:
Merge 98561 from mainline.
Avoid sibcall optimization if either caller or callee is using sret semantics.

Modified:
    llvm/branches/release_27/   (props changed)
    llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/release_27/lib/Target/X86/X86ISelLowering.h

Propchange: llvm/branches/release_27/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Mar 23 12:06:56 2010
@@ -1 +1 @@
-/llvm/trunk:97965,97974,97980,98171,98193,98203,98205,98212,98416
+/llvm/trunk:97965,97974,97980,98171,98193,98203,98205,98212,98416,98561

Modified: llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp?rev=99290&r1=99289&r2=99290&view=diff
==============================================================================
--- llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_27/lib/Target/X86/X86ISelLowering.cpp Tue Mar 23 12:06:56 2010
@@ -1477,7 +1477,6 @@
                                         DebugLoc dl,
                                         SelectionDAG &DAG,
                                         SmallVectorImpl<SDValue> &InVals) {
-
   MachineFunction &MF = DAG.getMachineFunction();
   X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
 
@@ -1779,7 +1778,8 @@
 
   if (isTailCall) {
     // Check if it's really possible to do a tail call.
-    isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
+    isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
+                    isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
                                                    Outs, Ins, DAG);
 
     // Sibcalls are automatically detected tailcalls which do not require
@@ -2297,6 +2297,8 @@
 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
                                                      CallingConv::ID CalleeCC,
                                                      bool isVarArg,
+                                                     bool isCalleeStructRet,
+                                                     bool isCallerStructRet,
                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
                                     const SmallVectorImpl<ISD::InputArg> &Ins,
                                                      SelectionDAG& DAG) const {
@@ -2316,10 +2318,15 @@
   // Look for obvious safe cases to perform tail call optimization that does not
   // requite ABI changes. This is what gcc calls sibcall.
 
-  // Do not tail call optimize vararg calls for now.
+  // Do not sibcall optimize vararg calls for now.
   if (isVarArg)
     return false;
 
+  // Also avoid sibcall optimization if either caller or callee uses struct
+  // return semantics.
+  if (isCalleeStructRet || isCallerStructRet)
+    return false;
+
   // If the callee takes no arguments then go on to check the results of the
   // call.
   if (!Outs.empty()) {

Modified: llvm/branches/release_27/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_27/lib/Target/X86/X86ISelLowering.h?rev=99290&r1=99289&r2=99290&view=diff
==============================================================================
--- llvm/branches/release_27/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/release_27/lib/Target/X86/X86ISelLowering.h Tue Mar 23 12:06:56 2010
@@ -637,6 +637,8 @@
     bool IsEligibleForTailCallOptimization(SDValue Callee,
                                            CallingConv::ID CalleeCC,
                                            bool isVarArg,
+                                           bool isCalleeStructRet,
+                                           bool isCallerStructRet,
                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
                                     const SmallVectorImpl<ISD::InputArg> &Ins,
                                            SelectionDAG& DAG) const;