[llvm-branch-commits] [llvm-branch] r105430 - in /llvm/branches/Apple/Troughton: ./ include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/X86/
Jakob Stoklund Olesen
stoklund at 2pi.dk
Thu Jun 3 16:14:11 PDT 2010
Author: stoklund
Date: Thu Jun 3 18:14:10 2010
New Revision: 105430
URL: http://llvm.org/viewvc/llvm-project?rev=105430&view=rev
Log:
Merge safe partial redef handling.
$ svn merge -c 105358 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r105358 into '.':
U include/llvm/Target/TargetInstrInfo.h
U include/llvm/CodeGen/MachineInstr.h
U lib/CodeGen/PreAllocSplitting.cpp
U lib/CodeGen/VirtRegRewriter.cpp
U lib/CodeGen/MachineInstr.cpp
U lib/CodeGen/SimpleRegisterCoalescing.cpp
U lib/CodeGen/TargetInstrInfoImpl.cpp
U lib/CodeGen/TwoAddressInstructionPass.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/ARM/ARMInstrInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.h
U lib/Target/ARM/ARMInstrInfo.h
$ svn merge -c 105361 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r105361 into '.':
G lib/CodeGen/SimpleRegisterCoalescing.cpp
$ svn merge -c 105369 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r105369 into '.':
U lib/CodeGen/LiveIntervalAnalysis.cpp
Modified:
llvm/branches/Apple/Troughton/ (props changed)
llvm/branches/Apple/Troughton/include/llvm/CodeGen/MachineInstr.h
llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h
llvm/branches/Apple/Troughton/lib/CodeGen/LiveIntervalAnalysis.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/MachineInstr.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/PreAllocSplitting.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/branches/Apple/Troughton/lib/CodeGen/VirtRegRewriter.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.cpp
llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.h
llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.h
Propchange: llvm/branches/Apple/Troughton/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Jun 3 18:14:10 2010
@@ -1 +1 @@
-/llvm/trunk:105399,105427
+/llvm/trunk:105358,105361,105369,105399,105427
Modified: llvm/branches/Apple/Troughton/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/include/llvm/CodeGen/MachineInstr.h?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/branches/Apple/Troughton/include/llvm/CodeGen/MachineInstr.h Thu Jun 3 18:14:10 2010
@@ -339,6 +339,11 @@
/// copyPredicates - Copies predicate operand(s) from MI.
void copyPredicates(const MachineInstr *MI);
+ /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
+ /// properly composing subreg indices where necessary.
+ void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
+ const TargetRegisterInfo &RegInfo);
+
/// addRegisterKilled - We have determined MI kills a register. Look for the
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
/// add a implicit operand if it's not found. Returns true if the operand
Modified: llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/include/llvm/Target/TargetInstrInfo.h Thu Jun 3 18:14:10 2010
@@ -194,11 +194,14 @@
/// reMaterialize - Re-issue the specified 'original' instruction at the
/// specific location targeting a new destination register.
+ /// The register in Orig->getOperand(0).getReg() will be substituted by
+ /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
+ /// SubIdx.
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const = 0;
+ const TargetRegisterInfo &TRI) const = 0;
/// duplicate - Create a duplicate of the Orig instruction in MF. This is like
/// MachineFunction::CloneMachineInstr(), but the target may update operands
@@ -585,7 +588,7 @@
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubReg,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const;
+ const TargetRegisterInfo &TRI) const;
virtual MachineInstr *duplicate(MachineInstr *Orig,
MachineFunction &MF) const;
virtual bool produceSameValue(const MachineInstr *MI0,
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Jun 3 18:14:10 2010
@@ -1098,7 +1098,6 @@
if (!mop.isReg())
continue;
unsigned Reg = mop.getReg();
- unsigned RegI = Reg;
if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg))
continue;
if (Reg != li.reg)
@@ -1140,26 +1139,8 @@
//
// Keep track of whether we replace a use and/or def so that we can
// create the spill interval with the appropriate range.
-
- HasUse = mop.isUse();
- HasDef = mop.isDef();
SmallVector<unsigned, 2> Ops;
- Ops.push_back(i);
- for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
- const MachineOperand &MOj = MI->getOperand(j);
- if (!MOj.isReg())
- continue;
- unsigned RegJ = MOj.getReg();
- if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ))
- continue;
- if (RegJ == RegI) {
- Ops.push_back(j);
- if (!MOj.isUndef()) {
- HasUse |= MOj.isUse();
- HasDef |= MOj.isDef();
- }
- }
- }
+ tie(HasUse, HasDef) = MI->readsWritesVirtualRegister(Reg, &Ops);
// Create a new virtual register for the spill interval.
// Create the new register now so we can map the fold instruction
@@ -1312,10 +1293,7 @@
struct RewriteInfo {
SlotIndex Index;
MachineInstr *MI;
- bool HasUse;
- bool HasDef;
- RewriteInfo(SlotIndex i, MachineInstr *mi, bool u, bool d)
- : Index(i), MI(mi), HasUse(u), HasDef(d) {}
+ RewriteInfo(SlotIndex i, MachineInstr *mi) : Index(i), MI(mi) {}
};
struct RewriteInfoCompare {
@@ -1394,7 +1372,7 @@
// easily see a situation where both registers are reloaded before
// the INSERT_SUBREG and both target registers that would overlap.
continue;
- RewriteMIs.push_back(RewriteInfo(index, MI, O.isUse(), O.isDef()));
+ RewriteMIs.push_back(RewriteInfo(index, MI));
}
std::sort(RewriteMIs.begin(), RewriteMIs.end(), RewriteInfoCompare());
@@ -1404,18 +1382,11 @@
RewriteInfo &rwi = RewriteMIs[i];
++i;
SlotIndex index = rwi.Index;
- bool MIHasUse = rwi.HasUse;
- bool MIHasDef = rwi.HasDef;
MachineInstr *MI = rwi.MI;
// If MI def and/or use the same register multiple times, then there
// are multiple entries.
- unsigned NumUses = MIHasUse;
while (i != e && RewriteMIs[i].MI == MI) {
assert(RewriteMIs[i].Index == index);
- bool isUse = RewriteMIs[i].HasUse;
- if (isUse) ++NumUses;
- MIHasUse |= isUse;
- MIHasDef |= RewriteMIs[i].HasDef;
++i;
}
MachineBasicBlock *MBB = MI->getParent();
@@ -1440,7 +1411,8 @@
// = use
// It's better to start a new interval to avoid artifically
// extend the new interval.
- if (MIHasDef && !MIHasUse) {
+ if (MI->readsWritesVirtualRegister(li.reg) ==
+ std::make_pair(false,true)) {
MBBVRegsMap.erase(MBB->getNumber());
ThisVReg = 0;
}
@@ -1674,19 +1646,9 @@
MachineInstr* MI = &*RI;
SmallVector<unsigned, 2> Indices;
- bool HasUse = false;
- bool HasDef = false;
-
- for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
- MachineOperand& mop = MI->getOperand(i);
- if (!mop.isReg() || mop.getReg() != li.reg) continue;
-
- HasUse |= MI->getOperand(i).isUse();
- HasDef |= MI->getOperand(i).isDef();
-
- Indices.push_back(i);
- }
-
+ bool HasUse, HasDef;
+ tie(HasUse, HasDef) = MI->readsWritesVirtualRegister(li.reg, &Indices);
+
if (!tryFoldMemoryOperand(MI, vrm, NULL, getInstructionIndex(MI),
Indices, true, slot, li.reg)) {
unsigned NewVReg = mri_->createVirtualRegister(rc);
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/MachineInstr.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/MachineInstr.cpp Thu Jun 3 18:14:10 2010
@@ -1037,6 +1037,29 @@
}
}
+void MachineInstr::substituteRegister(unsigned FromReg,
+ unsigned ToReg,
+ unsigned SubIdx,
+ const TargetRegisterInfo &RegInfo) {
+ if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
+ if (SubIdx)
+ ToReg = RegInfo.getSubReg(ToReg, SubIdx);
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = getOperand(i);
+ if (!MO.isReg() || MO.getReg() != FromReg)
+ continue;
+ MO.substPhysReg(ToReg, RegInfo);
+ }
+ } else {
+ for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = getOperand(i);
+ if (!MO.isReg() || MO.getReg() != FromReg)
+ continue;
+ MO.substVirtReg(ToReg, SubIdx, RegInfo);
+ }
+ }
+}
+
/// isSafeToMove - Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/PreAllocSplitting.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/PreAllocSplitting.cpp Thu Jun 3 18:14:10 2010
@@ -854,7 +854,7 @@
if (KillPt == DefMI->getParent()->end())
return false;
- TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI, TRI);
+ TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI, *TRI);
SlotIndex RematIdx = LIs->InsertMachineInstrInMaps(prior(RestorePt));
ReconstructLiveInterval(CurrLI);
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Jun 3 18:14:10 2010
@@ -727,7 +727,7 @@
MachineBasicBlock::iterator MII =
llvm::next(MachineBasicBlock::iterator(CopyMI));
- tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
+ tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_);
MachineInstr *NewMI = prior(MII);
if (checkForDeadDef) {
@@ -792,63 +792,63 @@
SubIdx = 0;
}
- // Copy the register use-list before traversing it. We may be adding operands
- // and invalidating pointers.
- SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
+ // Collect all the instructions using SrcReg.
+ SmallPtrSet<MachineInstr*, 32> Instrs;
for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
E = mri_->reg_end(); I != E; ++I)
- reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
+ Instrs.insert(&*I);
- for (unsigned N=0; N != reglist.size(); ++N) {
- MachineInstr *UseMI = reglist[N].first;
- MachineOperand &O = UseMI->getOperand(reglist[N].second);
- unsigned OldSubIdx = O.getSubReg();
- if (DstIsPhys) {
- unsigned UseDstReg = DstReg;
- if (OldSubIdx)
- UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
+ for (SmallPtrSet<MachineInstr*, 32>::const_iterator I = Instrs.begin(),
+ E = Instrs.end(); I != E; ++I) {
+ MachineInstr *UseMI = *I;
+ // A PhysReg copy that won't be coalesced can perhaps be rematerialized
+ // instead.
+ if (DstIsPhys) {
unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
CopySrcSubIdx, CopyDstSubIdx) &&
- CopySrcSubIdx == 0 &&
- CopyDstSubIdx == 0 &&
- CopySrcReg != CopyDstReg &&
- CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
- // If the use is a copy and it won't be coalesced away, and its source
- // is defined by a trivial computation, try to rematerialize it instead.
- if (!JoinedCopies.count(UseMI) &&
- ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
- CopyDstSubIdx, UseMI))
- continue;
- }
+ CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
+ CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
+ CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
+ ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
+ UseMI))
+ continue;
+ }
- O.setReg(UseDstReg);
- O.setSubReg(0);
- if (OldSubIdx) {
- // Def and kill of subregister of a virtual register actually defs and
- // kills the whole register. Add imp-defs and imp-kills as needed.
- if (O.isDef()) {
- if(O.isDead())
- UseMI->addRegisterDead(DstReg, tri_, true);
- else
- UseMI->addRegisterDefined(DstReg, tri_);
- } else if (!O.isUndef() &&
- (O.isKill() ||
- UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0))))
- UseMI->addRegisterKilled(DstReg, tri_, true);
- }
+ SmallVector<unsigned,8> Ops;
+ bool Reads, Writes;
+ tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
+ bool Kills = false, Deads = false;
+
+ // Replace SrcReg with DstReg in all UseMI operands.
+ for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+ MachineOperand &MO = UseMI->getOperand(Ops[i]);
+ Kills |= MO.isKill();
+ Deads |= MO.isDead();
+
+ if (DstIsPhys)
+ MO.substPhysReg(DstReg, *tri_);
+ else
+ MO.substVirtReg(DstReg, SubIdx, *tri_);
+ }
- DEBUG({
- dbgs() << "\t\tupdated: ";
- if (!UseMI->isDebugValue())
- dbgs() << li_->getInstructionIndex(UseMI) << "\t";
- dbgs() << *UseMI;
- });
+ // This instruction is a copy that will be removed.
+ if (JoinedCopies.count(UseMI))
continue;
- }
- O.substVirtReg(DstReg, SubIdx, *tri_);
+ if (SubIdx) {
+ // If UseMI was a simple SrcReg def, make sure we didn't turn it into a
+ // read-modify-write of DstReg.
+ if (Deads)
+ UseMI->addRegisterDead(DstReg, tri_);
+ else if (!Reads && Writes)
+ UseMI->addRegisterDefined(DstReg, tri_);
+
+ // Kill flags apply to the whole physical register.
+ if (DstIsPhys && Kills)
+ UseMI->addRegisterKilled(DstReg, tri_);
+ }
DEBUG({
dbgs() << "\t\tupdated: ";
@@ -857,15 +857,15 @@
dbgs() << *UseMI;
});
+
// After updating the operand, check if the machine instruction has
// become a copy. If so, update its val# information.
- if (JoinedCopies.count(UseMI))
+ const TargetInstrDesc &TID = UseMI->getDesc();
+ if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
continue;
- const TargetInstrDesc &TID = UseMI->getDesc();
unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
- if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
- tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
+ if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
CopySrcSubIdx, CopyDstSubIdx) &&
CopySrcReg != CopyDstReg &&
(TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/TargetInstrInfoImpl.cpp Thu Jun 3 18:14:10 2010
@@ -136,17 +136,9 @@
unsigned DestReg,
unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo &TRI) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
- MachineOperand &MO = MI->getOperand(0);
- if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
- MO.setReg(DestReg);
- MO.setSubReg(SubIdx);
- } else if (SubIdx) {
- MO.setReg(TRI->getSubReg(DestReg, SubIdx));
- } else {
- MO.setReg(DestReg);
- }
+ MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
}
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Jun 3 18:14:10 2010
@@ -1047,7 +1047,7 @@
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
- TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, TRI);
+ TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
ReMatRegs.set(regB);
++NumReMats;
} else {
Modified: llvm/branches/Apple/Troughton/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/CodeGen/VirtRegRewriter.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/CodeGen/VirtRegRewriter.cpp Thu Jun 3 18:14:10 2010
@@ -667,8 +667,7 @@
assert(TID.getNumDefs() == 1 &&
"Don't know how to remat instructions that define > 1 values!");
#endif
- TII->reMaterialize(MBB, MII, DestReg,
- ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI, TRI);
+ TII->reMaterialize(MBB, MII, DestReg, 0, ReMatDefMI, *TRI);
MachineInstr *NewMI = prior(MII);
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jun 3 18:14:10 2010
@@ -1212,17 +1212,12 @@
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const {
- if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
- DestReg = TRI->getSubReg(DestReg, SubIdx);
- SubIdx = 0;
- }
-
+ const TargetRegisterInfo &TRI) const {
unsigned Opcode = Orig->getOpcode();
switch (Opcode) {
default: {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
- MI->getOperand(0).setReg(DestReg);
+ MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
MBB.insert(I, MI);
break;
}
@@ -1238,9 +1233,6 @@
break;
}
}
-
- MachineInstr *NewMI = prior(I);
- NewMI->getOperand(0).setSubReg(SubIdx);
}
MachineInstr *
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMBaseInstrInfo.h Thu Jun 3 18:14:10 2010
@@ -300,7 +300,7 @@
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const;
+ const TargetRegisterInfo &TRI) const;
MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.cpp Thu Jun 3 18:14:10 2010
@@ -63,7 +63,7 @@
void ARMInstrInfo::
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo &TRI) const {
DebugLoc dl = Orig->getDebugLoc();
unsigned Opcode = Orig->getOpcode();
switch (Opcode) {
Modified: llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.h?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/lib/Target/ARM/ARMInstrInfo.h Thu Jun 3 18:14:10 2010
@@ -35,7 +35,7 @@
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const;
+ const TargetRegisterInfo &TRI) const;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
Modified: llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.cpp?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.cpp Thu Jun 3 18:14:10 2010
@@ -1064,14 +1064,9 @@
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const {
+ const TargetRegisterInfo &TRI) const {
DebugLoc DL = Orig->getDebugLoc();
- if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
- DestReg = TRI->getSubReg(DestReg, SubIdx);
- SubIdx = 0;
- }
-
// MOV32r0 etc. are implemented with xor which clobbers condition code.
// Re-materialize them as movri instructions to avoid side effects.
bool Clone = true;
@@ -1098,14 +1093,13 @@
if (Clone) {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
- MI->getOperand(0).setReg(DestReg);
MBB.insert(I, MI);
} else {
- BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
+ BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
}
MachineInstr *NewMI = prior(I);
- NewMI->getOperand(0).setSubReg(SubIdx);
+ NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
}
/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
Modified: llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.h?rev=105430&r1=105429&r2=105430&view=diff
==============================================================================
--- llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/Apple/Troughton/lib/Target/X86/X86InstrInfo.h Thu Jun 3 18:14:10 2010
@@ -555,7 +555,7 @@
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
- const TargetRegisterInfo *TRI) const;
+ const TargetRegisterInfo &TRI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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