[llvm-branch-commits] [llvm-branch] r109638 - in /llvm/branches/Apple/Hartnell: ./ lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h test/CodeGen/X86/vec_shift4.ll
Bill Wendling
isanbard at gmail.com
Wed Jul 28 12:57:52 PDT 2010
Author: void
Date: Wed Jul 28 14:57:52 2010
New Revision: 109638
URL: http://llvm.org/viewvc/llvm-project?rev=109638&view=rev
Log:
$ svn merge -c 109549 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r109549 into '.':
$ svn merge -c 109566 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r109566 into '.':
Added:
llvm/branches/Apple/Hartnell/test/CodeGen/X86/vec_shift4.ll
- copied, changed from r109549, llvm/trunk/test/CodeGen/X86/vec_shift4.ll
Modified:
llvm/branches/Apple/Hartnell/ (props changed)
llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.h
Propchange: llvm/branches/Apple/Hartnell/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jul 28 14:57:52 2010
@@ -1,2 +1,2 @@
/llvm/branches/Apple/Morbo:102475
-/llvm/trunk:104174-104175,105453,107846,108367,109519
+/llvm/trunk:104174-104175,105453,107846,108367,109519,109549
Modified: llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp?rev=109638&r1=109637&r2=109638&view=diff
==============================================================================
--- llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.cpp Wed Jul 28 14:57:52 2010
@@ -812,6 +812,10 @@
// FIXME: Do we need to handle scalar-to-vector here?
setOperationAction(ISD::MUL, MVT::v4i32, Legal);
+ // Can turn SHL into an integer multiply.
+ setOperationAction(ISD::SHL, MVT::v4i32, Custom);
+ setOperationAction(ISD::SHL, MVT::v16i8, Custom);
+
// i8 and i16 vectors are custom , because the source register and source
// source memory operand types are not the same width. f32 vectors are
// custom since the immediate controlling the insert encodes additional
@@ -7340,6 +7344,86 @@
return Res;
}
+SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
+ EVT VT = Op.getValueType();
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue R = Op.getOperand(0);
+
+ LLVMContext *Context = DAG.getContext();
+
+ assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
+
+ if (VT == MVT::v4i32) {
+ Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
+ Op.getOperand(1), DAG.getConstant(23, MVT::i32));
+
+ ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
+
+ std::vector<Constant*> CV(4, CI);
+ Constant *C = ConstantVector::get(CV);
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
+ SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
+ PseudoSourceValue::getConstantPool(), 0,
+ false, false, 16);
+
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
+ Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
+ Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
+ return DAG.getNode(ISD::MUL, dl, VT, Op, R);
+ }
+ if (VT == MVT::v16i8) {
+ // a = a << 5;
+ Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
+ Op.getOperand(1), DAG.getConstant(5, MVT::i32));
+
+ ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
+ ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
+
+ std::vector<Constant*> CVM1(16, CM1);
+ std::vector<Constant*> CVM2(16, CM2);
+ Constant *C = ConstantVector::get(CVM1);
+ SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
+ SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
+ PseudoSourceValue::getConstantPool(), 0,
+ false, false, 16);
+
+ // r = pblendv(r, psllw(r & (char16)15, 4), a);
+ M = DAG.getNode(ISD::AND, dl, VT, R, M);
+ M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
+ DAG.getConstant(4, MVT::i32));
+ R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
+ R, M, Op);
+ // a += a
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
+
+ C = ConstantVector::get(CVM2);
+ CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
+ M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
+ PseudoSourceValue::getConstantPool(), 0, false, false, 16);
+
+ // r = pblendv(r, psllw(r & (char16)63, 2), a);
+ M = DAG.getNode(ISD::AND, dl, VT, R, M);
+ M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
+ DAG.getConstant(2, MVT::i32));
+ R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
+ R, M, Op);
+ // a += a
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
+
+ // return pblendv(r, r+r, a);
+ R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
+ DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
+ R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
+ return R;
+ }
+ return SDValue();
+}
SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
// Lower the "add/sub/mul with overflow" instruction into a regular ins plus
@@ -7520,6 +7604,7 @@
case ISD::CTLZ: return LowerCTLZ(Op, DAG);
case ISD::CTTZ: return LowerCTTZ(Op, DAG);
case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
+ case ISD::SHL: return LowerSHL(Op, DAG);
case ISD::SADDO:
case ISD::UADDO:
case ISD::SSUBO:
Modified: llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.h?rev=109638&r1=109637&r2=109638&view=diff
==============================================================================
--- llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/Apple/Hartnell/lib/Target/X86/X86ISelLowering.h Wed Jul 28 14:57:52 2010
@@ -708,6 +708,7 @@
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
Copied: llvm/branches/Apple/Hartnell/test/CodeGen/X86/vec_shift4.ll (from r109549, llvm/trunk/test/CodeGen/X86/vec_shift4.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hartnell/test/CodeGen/X86/vec_shift4.ll?p2=llvm/branches/Apple/Hartnell/test/CodeGen/X86/vec_shift4.ll&p1=llvm/trunk/test/CodeGen/X86/vec_shift4.ll&r1=109549&r2=109638&rev=109638&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shift4.ll (original)
+++ llvm/branches/Apple/Hartnell/test/CodeGen/X86/vec_shift4.ll Wed Jul 28 14:57:52 2010
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=+sse41 | FileCheck %s
-define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
+define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
; CHECK-NOT: shll
; CHECK: pslld
@@ -12,3 +12,14 @@
%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2
}
+
+define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
+entry:
+; CHECK-NOT: shlb
+; CHECK: pblendvb
+; CHECK: pblendvb
+; CHECK: pblendvb
+ %shl = shl <16 x i8> %r, %a ; <<16 x i8>> [#uses=1]
+ %tmp2 = bitcast <16 x i8> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %tmp2
+}
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