[llvm-branch-commits] [llvm-branch] r92974 - in /llvm/branches/Apple/Zoidberg: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/anyext-uses.ll test/CodeGen/X86/fold-load.ll
Evan Cheng
evan.cheng at apple.com
Thu Jan 7 16:16:25 PST 2010
Author: evancheng
Date: Thu Jan 7 18:16:24 2010
New Revision: 92974
URL: http://llvm.org/viewvc/llvm-project?rev=92974&view=rev
Log:
Merge 92948 92950.
Removed:
llvm/branches/Apple/Zoidberg/test/CodeGen/X86/anyext-uses.ll
Modified:
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/Apple/Zoidberg/test/CodeGen/X86/fold-load.ll
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=92974&r1=92973&r2=92974&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 7 18:16:24 2010
@@ -1895,7 +1895,7 @@
? cast<LoadSDNode>(N0.getOperand(0))
: cast<LoadSDNode>(N0);
if (LN0->getExtensionType() != ISD::SEXTLOAD &&
- LN0->isUnindexed() && N0.hasOneUse()) {
+ LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
@@ -1903,71 +1903,51 @@
if (ExtVT == LoadedVT &&
(!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
- if (HasAnyExt) {
- SDValue Load =
- DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(),
- LN0->getValueType(0),
- LN0->getChain(), LN0->getBasePtr(),
- LN0->getSrcValue(), LN0->getSrcValueOffset(),
- ExtVT, LN0->isVolatile(), LN0->getAlignment());
- AddToWorkList(N);
- CombineTo(N0.getOperand(0).getNode(), Load, Load.getValue(1));
- return SDValue(N, 0); // Return N so it doesn't get rechecked!
- } else {
- SDValue Load =
- DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
- LN0->getChain(), LN0->getBasePtr(),
- LN0->getSrcValue(), LN0->getSrcValueOffset(),
- ExtVT, LN0->isVolatile(), LN0->getAlignment());
- AddToWorkList(N);
- CombineTo(N0.getNode(), Load, Load.getValue(1));
- return SDValue(N, 0); // Return N so it doesn't get rechecked!
- }
- } else if (!LN0->isVolatile()) {
- // Do not change the width of a volatile load.
- // Do not generate loads of non-round integer types since these can
- // be expensive (and would be wrong if the type is not byte sized).
- if (LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
- (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
- EVT PtrType = LN0->getOperand(1).getValueType();
-
- // For big endian targets, we need to add an offset to the pointer
- // to load the correct bytes. For little endian systems, we merely
- // need to read fewer bytes from the same pointer.
+ EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
+
+ SDValue NewLoad =
+ DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
+ LN0->getChain(), LN0->getBasePtr(),
+ LN0->getSrcValue(), LN0->getSrcValueOffset(),
+ ExtVT, LN0->isVolatile(), LN0->getAlignment());
+ AddToWorkList(N);
+ CombineTo(LN0, NewLoad, NewLoad.getValue(1));
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
+ }
+
+ // Do not change the width of a volatile load.
+ // Do not generate loads of non-round integer types since these can
+ // be expensive (and would be wrong if the type is not byte sized).
+ if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
+ (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
+ EVT PtrType = LN0->getOperand(1).getValueType();
+
+ unsigned Alignment = LN0->getAlignment();
+ SDValue NewPtr = LN0->getBasePtr();
+
+ // For big endian targets, we need to add an offset to the pointer
+ // to load the correct bytes. For little endian systems, we merely
+ // need to read fewer bytes from the same pointer.
+ if (TLI.isBigEndian()) {
unsigned LVTStoreBytes = LoadedVT.getStoreSize();
unsigned EVTStoreBytes = ExtVT.getStoreSize();
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
- unsigned Alignment = LN0->getAlignment();
- SDValue NewPtr = LN0->getBasePtr();
-
- if (TLI.isBigEndian()) {
- NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
- NewPtr, DAG.getConstant(PtrOff, PtrType));
- Alignment = MinAlign(Alignment, PtrOff);
- }
-
- AddToWorkList(NewPtr.getNode());
- if (HasAnyExt) {
- SDValue Load =
- DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(),
- LN0->getValueType(0),
- LN0->getChain(), NewPtr,
- LN0->getSrcValue(), LN0->getSrcValueOffset(),
- ExtVT, LN0->isVolatile(), Alignment);
- AddToWorkList(N);
- CombineTo(N0.getOperand(0).getNode(), Load, Load.getValue(1));
- return SDValue(N, 0); // Return N so it doesn't get rechecked!
- } else {
- SDValue Load =
- DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
- LN0->getChain(), NewPtr,
- LN0->getSrcValue(), LN0->getSrcValueOffset(),
- ExtVT, LN0->isVolatile(), Alignment);
- AddToWorkList(N);
- CombineTo(N0.getNode(), Load, Load.getValue(1));
- return SDValue(N, 0); // Return N so it doesn't get rechecked!
- }
+ NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
+ NewPtr, DAG.getConstant(PtrOff, PtrType));
+ Alignment = MinAlign(Alignment, PtrOff);
}
+
+ AddToWorkList(NewPtr.getNode());
+
+ EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
+ SDValue Load =
+ DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
+ LN0->getChain(), NewPtr,
+ LN0->getSrcValue(), LN0->getSrcValueOffset(),
+ ExtVT, LN0->isVolatile(), Alignment);
+ AddToWorkList(N);
+ CombineTo(LN0, Load, Load.getValue(1));
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
}
}
}
Removed: llvm/branches/Apple/Zoidberg/test/CodeGen/X86/anyext-uses.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/X86/anyext-uses.ll?rev=92973&view=auto
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/X86/anyext-uses.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/X86/anyext-uses.ll (removed)
@@ -1,47 +0,0 @@
-; RUN: llc < %s -march=x86-64 > %t
-; RUN: grep mov %t | count 8
-; RUN: not grep implicit %t
-
-; Avoid partial register updates; don't define an i8 register and read
-; the i32 super-register.
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
-target triple = "x86_64-apple-darwin9.6"
- %struct.RC4_KEY = type { i8, i8, [256 x i8] }
-
-define void @foo(%struct.RC4_KEY* nocapture %key, i64 %len, i8* %indata, i8* %outdata) nounwind {
-entry:
- br label %bb24
-
-bb24: ; preds = %bb24, %entry
- %0 = load i8* null, align 1 ; <i8> [#uses=1]
- %1 = zext i8 %0 to i64 ; <i64> [#uses=1]
- %2 = shl i64 %1, 32 ; <i64> [#uses=1]
- %3 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 0 ; <i8*> [#uses=1]
- %4 = load i8* %3, align 1 ; <i8> [#uses=2]
- %5 = add i8 %4, 0 ; <i8> [#uses=2]
- %6 = zext i8 %5 to i64 ; <i64> [#uses=0]
- %7 = load i8* null, align 1 ; <i8> [#uses=1]
- %8 = zext i8 %4 to i32 ; <i32> [#uses=1]
- %9 = zext i8 %7 to i32 ; <i32> [#uses=1]
- %10 = add i32 %9, %8 ; <i32> [#uses=1]
- %11 = and i32 %10, 255 ; <i32> [#uses=1]
- %12 = zext i32 %11 to i64 ; <i64> [#uses=1]
- %13 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 %12 ; <i8*> [#uses=1]
- %14 = load i8* %13, align 1 ; <i8> [#uses=1]
- %15 = zext i8 %14 to i64 ; <i64> [#uses=1]
- %16 = shl i64 %15, 48 ; <i64> [#uses=1]
- %17 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 0 ; <i8*> [#uses=1]
- %18 = load i8* %17, align 1 ; <i8> [#uses=2]
- %19 = add i8 %18, %5 ; <i8> [#uses=1]
- %20 = zext i8 %19 to i64 ; <i64> [#uses=1]
- %21 = getelementptr %struct.RC4_KEY* %key, i64 0, i32 2, i64 %20 ; <i8*> [#uses=1]
- store i8 %18, i8* %21, align 1
- %22 = or i64 0, %2 ; <i64> [#uses=1]
- %23 = or i64 %22, 0 ; <i64> [#uses=1]
- %24 = or i64 %23, %16 ; <i64> [#uses=1]
- %25 = or i64 %24, 0 ; <i64> [#uses=1]
- %26 = xor i64 %25, 0 ; <i64> [#uses=1]
- store i64 %26, i64* null, align 8
- br label %bb24
-}
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/X86/fold-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/X86/fold-load.ll?rev=92974&r1=92973&r2=92974&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/X86/fold-load.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/X86/fold-load.ll Thu Jan 7 18:16:24 2010
@@ -1,11 +1,12 @@
-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 | FileCheck %s
%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
%struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (...)*, void (...)*, i8*, i8 }
@stmt_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=1]
-define void @expand_start_bindings() {
+; This should just not crash.
+define void @test1() nounwind {
entry:
- br i1 false, label %cond_true, label %cond_next
+ br i1 true, label %cond_true, label %cond_next
cond_true: ; preds = %entry
%new_size.0.i = select i1 false, i32 0, i32 0 ; <i32> [#uses=1]
@@ -25,3 +26,22 @@
cond_next: ; preds = %entry
ret void
}
+
+
+
+define i32 @test2(i16* %P, i16* %Q) nounwind {
+ %A = load i16* %P, align 4 ; <i16> [#uses=11]
+ %C = zext i16 %A to i32 ; <i32> [#uses=1]
+ %D = and i32 %C, 255 ; <i32> [#uses=1]
+ br label %L
+L:
+
+ store i16 %A, i16* %Q
+ ret i32 %D
+
+; CHECK: test2:
+; CHECK: movl 4(%esp), %eax
+; CHECK-NEXT: movzwl (%eax), %ecx
+
+}
+
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