[llvm-branch-commits] [llvm-branch] r101517 - in /llvm/branches/Apple/Morbo: ./ lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td

Eric Christopher echristo at apple.com
Fri Apr 16 11:39:55 PDT 2010


Author: echristo
Date: Fri Apr 16 13:39:55 2010
New Revision: 101517

URL: http://llvm.org/viewvc/llvm-project?rev=101517&view=rev
Log:
Merge r101331 from mainline.

Partially fixes 7349371.

Modified:
    llvm/branches/Apple/Morbo/   (props changed)
    llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
    llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrSSE.td

Propchange: llvm/branches/Apple/Morbo/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Apr 16 13:39:55 2010
@@ -1,2 +1,2 @@
 /llvm/branches/Apple/Hermes:96832,96835,96858,96870,96876,96879
-/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100056,100072,100074,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100332,100353,100384,100454-100455,100457,100478,100480,100487,100494,100497,100505,100521,100553,100568,100584,100592,100609-100610,100636,100710,100736,100742,100751,100768-100769,100771,100781,100797,100804,10
 0837,100867,100892,100936-100937,101011,101023,101075,101077,101079,101081,101085,101154,101158,101162,101165,101181,101190,101202,101282,101303,101314-101315,101317,101343,101383,101392,101420,101453
+/llvm/trunk:98602,98604,98612,98615-98616,98675,98686,98743-98744,98768,98773,98778,98780,98810,98835,98839,98845,98855,98862,98881,98920,98977,99032-99033,99043,99196,99223,99263,99282-99284,99306,99319-99321,99324,99336,99378,99418,99423,99429,99455,99463,99465,99469,99484,99490,99492-99494,99507,99524,99537,99539-99540,99544,99570,99575,99598,99620,99629-99630,99636,99671,99692,99695,99697,99699,99722,99816,99836,99845-99846,99848,99850,99855,99879,99881-99883,99895,99899,99910,99916,99919,99952-99954,99957,99959,99974-99975,99982,99984-99986,99988,99992-99993,99995,99997-99999,100016,100035,100037-100038,100042,100044,100056,100072,100074,100081-100090,100092,100094-100095,100116,100134,100184,100209,100214-100218,100220-100221,100223-100225,100257,100261,100304,100332,100353,100384,100454-100455,100457,100478,100480,100487,100494,100497,100505,100521,100553,100568,100584,100592,100609-100610,100636,100710,100736,100742,100751,100768-100769,100771,100781,100797,100804,10
 0837,100867,100892,100936-100937,101011,101023,101075,101077,101079,101081,101085,101154,101158,101162,101165,101181,101190,101202,101282,101303,101314-101315,101317,101331,101343,101383,101392,101420,101453

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp?rev=101517&r1=101516&r2=101517&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86ISelLowering.cpp Fri Apr 16 13:39:55 2010
@@ -7933,9 +7933,9 @@
 bool
 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
                                       EVT VT) const {
-  // Only do shuffles on 128-bit vector types for now.
+  // Very little shuffling can be done for 64-bit vectors right now.
   if (VT.getSizeInBits() == 64)
-    return false;
+    return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
 
   // FIXME: pshufb, blends, shifts.
   return (VT.getVectorNumElements() == 2 ||

Modified: llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrSSE.td?rev=101517&r1=101516&r2=101517&view=diff
==============================================================================
--- llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/Apple/Morbo/lib/Target/X86/X86InstrSSE.td Fri Apr 16 13:39:55 2010
@@ -2916,6 +2916,7 @@
                                         int_x86_ssse3_psign_d,
                                         int_x86_ssse3_psign_d_128>;
 
+// palignr patterns.
 let Constraints = "$src1 = $dst" in {
   def PALIGNR64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, VR64:$src2, i8imm:$src3),
@@ -2936,7 +2937,6 @@
                            []>, OpSize;
 }
 
-// palignr patterns.
 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
           (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
           Requires<[HasSSSE3]>;
@@ -2945,6 +2945,26 @@
                                       (i8 imm:$src3)),
           (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
           Requires<[HasSSSE3]>;
+def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
+          (PALIGNR64rr VR64:$src2, VR64:$src1,
+                       (SHUFFLE_get_palign_imm VR64:$src3))>,
+          Requires<[HasSSSE3]>;
+def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
+          (PALIGNR64rr VR64:$src2, VR64:$src1,
+                       (SHUFFLE_get_palign_imm VR64:$src3))>,
+          Requires<[HasSSSE3]>;
+def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
+          (PALIGNR64rr VR64:$src2, VR64:$src1,
+                       (SHUFFLE_get_palign_imm VR64:$src3))>,
+          Requires<[HasSSSE3]>;
+def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
+          (PALIGNR64rr VR64:$src2, VR64:$src1,
+                       (SHUFFLE_get_palign_imm VR64:$src3))>,
+          Requires<[HasSSSE3]>;
+def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
+          (PALIGNR64rr VR64:$src2, VR64:$src1,
+                       (SHUFFLE_get_palign_imm VR64:$src3))>,
+          Requires<[HasSSSE3]>;
 
 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
           (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,





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