[llvm-branch-commits] [llvm-branch] r101289 - in /llvm/branches/Apple/Hermes: ./ lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2010-04-14-SplitVector.ll

[Bob Wilson]

Author: bwilson
Date: Wed Apr 14 16:02:14 2010
New Revision: 101289

URL: http://llvm.org/viewvc/llvm-project?rev=101289&view=rev
Log:
--- Merging r101282 into '.':
A    test/CodeGen/ARM/2010-04-14-SplitVector.ll
U    lib/Target/ARM/ARMISelLowering.cpp

Added:
    llvm/branches/Apple/Hermes/test/CodeGen/ARM/2010-04-14-SplitVector.ll
      - copied unchanged from r101282, llvm/trunk/test/CodeGen/ARM/2010-04-14-SplitVector.ll
Modified:
    llvm/branches/Apple/Hermes/   (props changed)
    llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp

Propchange: llvm/branches/Apple/Hermes/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Apr 14 16:02:14 2010
@@ -1 +1 @@
-/llvm/trunk:96521,96525,96572,96621,96775,96825,96827,96990,97025,97065,97071,97538,97707,97757,97782,97797,98210,98270,98395,98398,98402,98409,98416,98427,98561,98586,98845,98977,99043,99630,99678,100568,100892,101181
+/llvm/trunk:96521,96525,96572,96621,96775,96825,96827,96990,97025,97065,97071,97538,97707,97757,97782,97797,98210,98270,98395,98398,98402,98409,98416,98427,98561,98586,98845,98977,99043,99630,99678,100568,100892,101181,101282

Modified: llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp?rev=101289&r1=101288&r2=101289&view=diff
==============================================================================
--- llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Hermes/lib/Target/ARM/ARMISelLowering.cpp Wed Apr 14 16:02:14 2010
@@ -2113,6 +2113,13 @@
 
 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
   SDValue Op = N->getOperand(0);
+
+  // Do not create a VMOVDRR or VMOVRRD node if the operand type is not
+  // legal.  The legalizer won't know what to do with that.
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  if (!TLI.isTypeLegal(Op.getValueType()))
+    return SDValue();
+
   DebugLoc dl = N->getDebugLoc();
   if (N->getValueType(0) == MVT::f64) {
     // Turn i64->f64 into VMOVDRR.
@@ -3060,21 +3067,21 @@
 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
                                            SmallVectorImpl<SDValue>&Results,
                                            SelectionDAG &DAG) {
+  SDValue Res;
   switch (N->getOpcode()) {
   default:
     llvm_unreachable("Don't know how to custom expand this!");
-    return;
+    break;
   case ISD::BIT_CONVERT:
-    Results.push_back(ExpandBIT_CONVERT(N, DAG));
-    return;
+    Res = ExpandBIT_CONVERT(N, DAG);
+    break;
   case ISD::SRL:
-  case ISD::SRA: {
-    SDValue Res = LowerShift(N, DAG, Subtarget);
-    if (Res.getNode())
-      Results.push_back(Res);
-    return;
-  }
+  case ISD::SRA:
+    Res = LowerShift(N, DAG, Subtarget);
+    break;
   }
+  if (Res.getNode())
+    Results.push_back(Res);
 }
 
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