[llvm-branch-commits] [llvm-branch] r83076 - in /llvm/branches/Apple/Leela: lib/CodeGen/LLVMTargetMachine.cpp test/CodeGen/ARM/2009-08-21-PostRAKill.ll test/CodeGen/ARM/2009-08-21-PostRAKill2.ll test/CodeGen/ARM/2009-08-21-PostRAKill3.ll test/CodeGen/ARM/2009-08-21-PostRAKill4.ll test/CodeGen/X86/break-anti-dependencies.ll
Bob Wilson
bob.wilson at apple.com
Tue Sep 29 10:18:50 PDT 2009
Author: bwilson
Date: Tue Sep 29 12:18:50 2009
New Revision: 83076
URL: http://llvm.org/viewvc/llvm-project?rev=83076&view=rev
Log:
$ svn merge -c 82803 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r82803 into '.':
U test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
U test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
U test/CodeGen/ARM/2009-08-21-PostRAKill.ll
U test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
U test/CodeGen/X86/break-anti-dependencies.ll
U lib/CodeGen/LLVMTargetMachine.cpp
Modified:
llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/break-anti-dependencies.ll
Modified: llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp?rev=83076&r1=83075&r2=83076&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/LLVMTargetMachine.cpp Tue Sep 29 12:18:50 2009
@@ -43,11 +43,13 @@
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
-// When this works it will be on by default.
+// This is not enabled by default due to 1) high compile time cost, 2) it's not
+// beneficial to all targets. The plan is to let targets decide whether this
+// is enabled.
static cl::opt<bool>
-DisablePostRAScheduler("disable-post-RA-scheduler",
- cl::desc("Disable scheduling after register allocation"),
- cl::init(true));
+EnablePostRAScheduler("post-RA-scheduler",
+ cl::desc("Enable scheduling after register allocation"),
+ cl::init(false));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
@@ -319,7 +321,7 @@
printAndVerify(PM);
// Second pass scheduler.
- if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
+ if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
PM.add(createPostRAScheduler());
printAndVerify(PM);
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll?rev=83076&r1=83075&r2=83076&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill.ll Tue Sep 29 12:18:50 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -post-RA-scheduler -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll?rev=83076&r1=83075&r2=83076&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll Tue Sep 29 12:18:50 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll?rev=83076&r1=83075&r2=83076&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll Tue Sep 29 12:18:50 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll?rev=83076&r1=83075&r2=83076&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll Tue Sep 29 12:18:50 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/break-anti-dependencies.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/break-anti-dependencies.ll?rev=83076&r1=83075&r2=83076&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/break-anti-dependencies.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/break-anti-dependencies.ll Tue Sep 29 12:18:50 2009
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies=false > %t
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t
; RUN: grep {%xmm0} %t | count 14
; RUN: not grep {%xmm1} %t
-; RUN: llc < %s -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies > %t
+; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t
; RUN: grep {%xmm0} %t | count 7
; RUN: grep {%xmm1} %t | count 7
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