[llvm-branch-commits] [llvm-branch] r83005 - in /llvm/branches/eh-experiment: include/llvm/CodeGen/SelectionDAGNodes.h include/llvm/Intrinsics.td lib/CodeGen/IntrinsicLowering.cpp lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp
Bill Wendling
isanbard at gmail.com
Mon Sep 28 12:10:38 PDT 2009
Author: void
Date: Mon Sep 28 14:10:38 2009
New Revision: 83005
URL: http://llvm.org/viewvc/llvm-project?rev=83005&view=rev
Log:
Initial check-in for the new "llvm.eh.personality" intrinsic. Almost certainly
incorrect, but it can be refined/corrected while we implement this heretical
exception handling schema. :-)
Modified:
llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/branches/eh-experiment/include/llvm/Intrinsics.td
llvm/branches/eh-experiment/lib/CodeGen/IntrinsicLowering.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/eh-experiment/include/llvm/CodeGen/SelectionDAGNodes.h Mon Sep 28 14:10:38 2009
@@ -126,6 +126,10 @@
// the selection index of the exception thrown.
EHSELECTION,
+ // RESULT, OUTCHAIN = EHPERSONALITY(INCHAIN, EXCEPTION) - This node
+ // represents the selection index of the exception thrown.
+ EHPERSONALITY,
+
// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
// 'eh_return' gcc dwarf builtin, which is used to return from
// exception. The general meaning is: adjust stack by OFFSET and pass
Modified: llvm/branches/eh-experiment/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/include/llvm/Intrinsics.td?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/include/llvm/Intrinsics.td (original)
+++ llvm/branches/eh-experiment/include/llvm/Intrinsics.td Mon Sep 28 14:10:38 2009
@@ -289,7 +289,11 @@
//===------------------ Exception Handling Intrinsics----------------------===//
//
+def int_eh_personality_i32 : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
+def int_eh_personality_i64 : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty]>;
+
def int_eh_exception : Intrinsic<[llvm_ptr_ty]>;
+
def int_eh_selector_i32 : Intrinsic<[llvm_i32_ty],
[llvm_ptr_ty, llvm_ptr_ty, llvm_vararg_ty]>;
def int_eh_selector_i64 : Intrinsic<[llvm_i64_ty],
Modified: llvm/branches/eh-experiment/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/IntrinsicLowering.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/IntrinsicLowering.cpp Mon Sep 28 14:10:38 2009
@@ -437,6 +437,8 @@
case Intrinsic::eh_exception:
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64:
+ case Intrinsic::eh_personality_i32:
+ case Intrinsic::eh_personality_i64:
CI->replaceAllUsesWith(Constant::getNullValue(CI->getType()));
break;
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Sep 28 14:10:38 2009
@@ -447,8 +447,7 @@
switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
default: break;
case TargetLowering::Expand: {
- EVT VT = (IID == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (IID == Intrinsic::eh_selector_i32 ? MVT::i32 : MVT::i64);
if (MMI) {
if (MBB->isLandingPad())
@@ -480,6 +479,37 @@
}
break;
}
+
+ case Intrinsic::eh_personality_i32:
+ case Intrinsic::eh_personality_i64: {
+ EVT VT = TLI.getValueType(I->getType());
+ switch (TLI.getOperationAction(ISD::EHPERSONALITY, VT)) {
+ default: break;
+ case TargetLowering::Expand: {
+ EVT VT = (IID == Intrinsic::eh_personality_i32 ? MVT::i32 : MVT::i64);
+
+ if (MMI) {
+ // FIXME: Mark exception selector register as live in. Hack for PR1508.
+ unsigned Reg = TLI.getExceptionSelectorRegister();
+ if (Reg) MBB->addLiveIn(Reg);
+
+ const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
+ unsigned ResultReg = createResultReg(RC);
+ bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
+ Reg, RC, RC);
+ assert(InsertedCopy && "Can't copy address registers!");
+ InsertedCopy = InsertedCopy;
+ UpdateValueMap(I, ResultReg);
+ } else {
+ unsigned ResultReg =
+ getRegForValue(Constant::getNullValue(I->getType()));
+ UpdateValueMap(I, ResultReg);
+ }
+ return true;
+ }
+ }
+ break;
+ }
}
return false;
}
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Sep 28 14:10:38 2009
@@ -2599,6 +2599,14 @@
Results.push_back(Results[0].getValue(1));
break;
}
+ case ISD::EHPERSONALITY: {
+ unsigned Reg = TLI.getExceptionSelectorRegister();
+ assert(Reg && "Can't expand to unknown register!");
+ Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
+ Node->getValueType(0)));
+ Results.push_back(Results[0].getValue(1));
+ break;
+ }
case ISD::EXCEPTIONADDR: {
unsigned Reg = TLI.getExceptionAddressRegister();
assert(Reg && "Can't expand to unknown register!");
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Sep 28 14:10:38 2009
@@ -5367,6 +5367,7 @@
case ISD::EXCEPTIONADDR: return "EXCEPTIONADDR";
case ISD::LSDAADDR: return "LSDAADDR";
case ISD::EHSELECTION: return "EHSELECTION";
+ case ISD::EHPERSONALITY: return "EHPERSONALITY";
case ISD::EH_RETURN: return "EH_RETURN";
case ISD::ConstantPool: return "ConstantPool";
case ISD::ExternalSymbol: return "ExternalSymbol";
Modified: llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp (original)
+++ llvm/branches/eh-experiment/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp Mon Sep 28 14:10:38 2009
@@ -4033,6 +4033,34 @@
return 0;
}
+ case Intrinsic::eh_personality_i32:
+ case Intrinsic::eh_personality_i64: {
+ MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
+
+ // FIXME: Mark exception selector register as live in. Hack for PR1508.
+ unsigned Reg = TLI.getExceptionSelectorRegister();
+ if (Reg) CurMBB->addLiveIn(Reg);
+
+ // Insert the EHPERSONALITY instruction.
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDValue Ops[2];
+ Ops[0] = getValue(I.getOperand(1));
+ Ops[1] = getRoot();
+ SDValue Op = DAG.getNode(ISD::EHPERSONALITY, dl, VTs, Ops, 2);
+
+ DAG.setRoot(Op.getValue(1));
+
+ MVT::SimpleValueType VT =
+ (Intrinsic == Intrinsic::eh_personality_i32 ? MVT::i32 : MVT::i64);
+ if (Op.getValueType().getSimpleVT() < VT)
+ Op = DAG.getNode(ISD::SIGN_EXTEND, dl, VT, Op);
+ else if (Op.getValueType().getSimpleVT() < VT)
+ Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
+
+ setValue(&I, Op);
+ return 0;
+ }
+
case Intrinsic::eh_typeid_for_i32:
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
Modified: llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/Target/ARM/ARMISelLowering.cpp Mon Sep 28 14:10:38 2009
@@ -371,6 +371,7 @@
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
+ setOperationAction(ISD::EHPERSONALITY, MVT::i32, Expand);
// FIXME: Shouldn't need this, since no register is used, but the legalizer
// doesn't yet know how to not do that for SjLj.
setExceptionSelectorRegister(ARM::R0);
Modified: llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/Target/PowerPC/PPCISelLowering.cpp Mon Sep 28 14:10:38 2009
@@ -188,9 +188,10 @@
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+ setOperationAction(ISD::EHPERSONALITY, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
-
+ setOperationAction(ISD::EHPERSONALITY, MVT::i32, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
Modified: llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp?rev=83005&r1=83004&r2=83005&view=diff
==============================================================================
--- llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/eh-experiment/lib/Target/X86/X86ISelLowering.cpp Mon Sep 28 14:10:38 2009
@@ -383,8 +383,11 @@
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
+ setOperationAction(ISD::EHPERSONALITY, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
+ setOperationAction(ISD::EHPERSONALITY, MVT::i32, Expand);
+
if (Subtarget->is64Bit()) {
setExceptionPointerRegister(X86::RAX);
setExceptionSelectorRegister(X86::RDX);
More information about the llvm-branch-commits
mailing list