[llvm-branch-commits] [llvm-branch] r89685 - in /llvm/branches/Apple/Zoidberg: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/PowerPC/PPCISelDAGToDAG.cpp test/CodeGen/PowerPC/rlwimi-keep-rsh.ll test/CodeGen/PowerPC/vec_buildvector_loadstore.ll

[Bill Wendling]

Author: void
Date: Mon Nov 23 12:35:12 2009
New Revision: 89685

URL: http://llvm.org/viewvc/llvm-project?rev=89685&view=rev
Log:
$ svn merge -c 89496 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r89496 into '.':
A    test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
U    lib/Target/PowerPC/PPCISelDAGToDAG.cpp
$ svn merge -c 89521 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r89521 into '.':
A    test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
U    lib/CodeGen/SelectionDAG/LegalizeDAG.cpp


Added:
    llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
      - copied unchanged from r89496, llvm/trunk/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
    llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
      - copied unchanged from r89521, llvm/trunk/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll
Modified:
    llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=89685&r1=89684&r2=89685&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 23 12:35:12 2009
@@ -1517,6 +1517,7 @@
   // Create the stack frame object.
   EVT VT = Node->getValueType(0);
   EVT OpVT = Node->getOperand(0).getValueType();
+  EVT EltVT = VT.getVectorElementType();
   DebugLoc dl = Node->getDebugLoc();
   SDValue FIPtr = DAG.CreateStackTemporary(VT);
   int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
@@ -1524,7 +1525,7 @@
 
   // Emit a store of each element to the stack slot.
   SmallVector<SDValue, 8> Stores;
-  unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
+  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
   // Store (in the right endianness) the elements to memory.
   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
     // Ignore undef elements.
@@ -1535,8 +1536,13 @@
     SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
     Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
 
-    Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
-                                  Idx, SV, Offset));
+    // If EltVT smaller than OpVT, only store the bits necessary.
+    if (EltVT.bitsLT(OpVT))
+      Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
+                          Node->getOperand(i), Idx, SV, Offset, EltVT));
+    else
+      Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 
+                                    Node->getOperand(i), Idx, SV, Offset));
   }
 
   SDValue StoreChain;

Modified: llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=89685&r1=89684&r2=89685&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Nov 23 12:35:12 2009
@@ -443,8 +443,7 @@
     
     unsigned MB, ME;
     if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
-      SDValue Tmp1, Tmp2, Tmp3;
-      bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
+      SDValue Tmp1, Tmp2;
 
       if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
           isInt32Immediate(Op1.getOperand(1), Value)) {
@@ -461,10 +460,9 @@
           Op1 = Op1.getOperand(0);
         }
       }
-      
-      Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
+
       SH &= 31;
-      SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
+      SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
                           getI32Imm(ME) };
       return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
     }