[llvm-branch-commits] [llvm-branch] r86063 - in /llvm/branches/Apple/Leela: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMConstantPoolValue.h lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h lib/Target/PowerPC/PPCInstr64Bit.td lib/Target/PowerPC/PPCInstrInfo.td test/CodeGen/ARM/indirectbr.ll test/CodeGen/PowerPC/indirectbr.ll
Bill Wendling
isanbard at gmail.com
Wed Nov 4 15:07:25 PST 2009
Author: void
Date: Wed Nov 4 17:07:25 2009
New Revision: 86063
URL: http://llvm.org/viewvc/llvm-project?rev=86063&view=rev
Log:
$ svn merge -c 85878 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85878 into '.':
U lib/Target/ARM/ARMBaseInstrInfo.cpp
$ svn merge -c 86056 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86056 into '.':
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 86057 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86057 into '.':
G lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 85805 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85805 into '.':
U lib/Target/ARM/ARMISelDAGToDAG.cpp
$ svn merge -c 85808 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85808 into '.':
U lib/Target/ARM/ARMConstantPoolValue.h
$ svn merge -c 86042 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86042 into '.':
A test/CodeGen/ARM/indirectbr.ll
$ svn merge -c 86045 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86045 into '.':
U test/CodeGen/ARM/indirectbr.ll
$ svn merge -c 86050 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86050 into '.':
A test/CodeGen/PowerPC/indirectbr.ll
U lib/Target/PowerPC/PPCISelLowering.h
U lib/Target/PowerPC/PPCInstr64Bit.td
U lib/Target/PowerPC/PPCInstrInfo.td
U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
U lib/Target/PowerPC/PPCISelLowering.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/ARM/indirectbr.ll
- copied, changed from r86042, llvm/trunk/test/CodeGen/ARM/indirectbr.ll
llvm/branches/Apple/Leela/test/CodeGen/PowerPC/indirectbr.ll
- copied unchanged from r86050, llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantPoolValue.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/Apple/Leela/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.h
llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstrInfo.td
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Nov 4 17:07:25 2009
@@ -23,7 +23,6 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/CommandLine.h"
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Nov 4 17:07:25 2009
@@ -514,6 +514,7 @@
unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
return (RealignStack &&
!AFI->isThumb1OnlyFunction() &&
+ AFI->hasStackFrame() &&
(MFI->getMaxAlignment() > StackAlign) &&
!MFI->hasVarSizedObjects());
}
@@ -1339,10 +1340,10 @@
AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
+ movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
NumBytes = DPRCSOffset;
if (NumBytes) {
- // Insert it after all the callee-save spills.
- movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI);
+ // Adjust SP after all the callee-save spills.
emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantPoolValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantPoolValue.h?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantPoolValue.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantPoolValue.h Wed Nov 4 17:07:25 2009
@@ -33,14 +33,14 @@
}
/// ARMConstantPoolValue - ARM specific constantpool value. This is used to
-/// represent PC relative displacement between the address of the load
+/// represent PC-relative displacement between the address of the load
/// instruction and the constant being loaded, i.e. (&GV-(LPIC+8)).
class ARMConstantPoolValue : public MachineConstantPoolValue {
Constant *CVal; // Constant being loaded.
const char *S; // ExtSymbol being loaded.
unsigned LabelId; // Label id of the load.
ARMCP::ARMCPKind Kind; // Kind of constant.
- unsigned char PCAdjust; // Extra adjustment if constantpool is pc relative.
+ unsigned char PCAdjust; // Extra adjustment if constantpool is pc-relative.
// 8 for ARM, 4 for Thumb.
const char *Modifier; // GV modifier i.e. (&GV(modifier)-(LPIC+8))
bool AddCurrentAddress;
@@ -86,7 +86,6 @@
void dump() const;
};
-
inline raw_ostream &operator<<(raw_ostream &O, const ARMConstantPoolValue &V) {
V.print(O);
return O;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Nov 4 17:07:25 2009
@@ -13,7 +13,6 @@
#include "ARM.h"
#include "ARMAddressingModes.h"
-#include "ARMConstantPoolValue.h"
#include "ARMISelLowering.h"
#include "ARMTargetMachine.h"
#include "llvm/CallingConv.h"
Modified: llvm/branches/Apple/Leela/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Wed Nov 4 17:07:25 2009
@@ -414,6 +414,9 @@
O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
<< '_' << MO.getIndex();
return;
+ case MachineOperand::MO_BlockAddress:
+ GetBlockAddressSymbol(MO.getBlockAddress())->print(O, MAI);
+ return;
case MachineOperand::MO_ExternalSymbol: {
// Computing the address of an external symbol, not calling it.
std::string Name(MAI->getGlobalPrefix());
Modified: llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.cpp?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 4 17:07:25 2009
@@ -196,10 +196,12 @@
// appropriate instructions to materialize the address.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
+ setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
+ setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
@@ -1167,6 +1169,36 @@
return SDValue(); // Not reached
}
+SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
+ EVT PtrVT = Op.getValueType();
+ DebugLoc DL = Op.getDebugLoc();
+
+ BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
+ SDValue TgtBA = DAG.getBlockAddress(BA, DL, /*isTarget=*/true);
+ SDValue Zero = DAG.getConstant(0, PtrVT);
+ SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero);
+ SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero);
+
+ // If this is a non-darwin platform, we don't support non-static relo models
+ // yet.
+ const TargetMachine &TM = DAG.getTarget();
+ if (TM.getRelocationModel() == Reloc::Static ||
+ !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
+ // Generate non-pic code that has direct accesses to globals.
+ // The address of the global is just (hi(&g)+lo(&g)).
+ return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
+ }
+
+ if (TM.getRelocationModel() == Reloc::PIC_) {
+ // With PIC, the first instruction is actually "GR+hi(&G)".
+ Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
+ DAG.getNode(PPCISD::GlobalBaseReg,
+ DebugLoc::getUnknownLoc(), PtrVT), Hi);
+ }
+
+ return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
+}
+
SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) {
EVT PtrVT = Op.getValueType();
@@ -4181,6 +4213,7 @@
switch (Op.getOpcode()) {
default: llvm_unreachable("Wasn't expecting to be able to lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
+ case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Modified: llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.h?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCISelLowering.h Wed Nov 4 17:07:25 2009
@@ -361,6 +361,7 @@
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
+ SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
Modified: llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstr64Bit.td?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstr64Bit.td Wed Nov 4 17:07:25 2009
@@ -731,9 +731,13 @@
def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
+def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
+def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
(ADDIS8 G8RC:$in, tglobaladdr:$g)>;
def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS8 G8RC:$in, tconstpool:$g)>;
def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
(ADDIS8 G8RC:$in, tjumptable:$g)>;
+def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
+ (ADDIS8 G8RC:$in, tblockaddress:$g)>;
Modified: llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstrInfo.td?rev=86063&r1=86062&r2=86063&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/PowerPC/PPCInstrInfo.td Wed Nov 4 17:07:25 2009
@@ -1436,12 +1436,16 @@
def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
+def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
+def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
(ADDIS GPRC:$in, tglobaladdr:$g)>;
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS GPRC:$in, tconstpool:$g)>;
def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
(ADDIS GPRC:$in, tjumptable:$g)>;
+def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
+ (ADDIS GPRC:$in, tblockaddress:$g)>;
// Fused negative multiply subtract, alternate pattern
def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
Copied: llvm/branches/Apple/Leela/test/CodeGen/ARM/indirectbr.ll (from r86042, llvm/trunk/test/CodeGen/ARM/indirectbr.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/indirectbr.ll?p2=llvm/branches/Apple/Leela/test/CodeGen/ARM/indirectbr.ll&p1=llvm/trunk/test/CodeGen/ARM/indirectbr.ll&r1=86042&r2=86063&rev=86063&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/indirectbr.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/indirectbr.ll Wed Nov 4 17:07:25 2009
@@ -47,10 +47,10 @@
; ARM: ldr r1, LCPI1_2
; ARM: add r1, pc, r1
; ARM: str r1
-; THUMB: ldr r2, LCPI1_4
+; THUMB: ldr.n r2, LCPI1_4
; THUMB: add r2, pc
; THUMB: str r2
-; THUMB2: ldr r2, LCPI1_2
+; THUMB2: ldr.n r2, LCPI1_2
; THUMB2-NEXT: str r2
store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
ret i32 %res.3
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