[llvm-branch-commits] [llvm-branch] r92059 - in /llvm/branches/Apple/Zoidberg/lib: CodeGen/SimpleRegisterCoalescing.cpp Target/ARM/ARMInstrThumb.td Target/ARM/ARMRegisterInfo.td

[Jakob Stoklund Olesen]

Author: stoklund
Date: Wed Dec 23 15:48:12 2009
New Revision: 92059

URL: http://llvm.org/viewvc/llvm-project?rev=92059&view=rev
Log:
Merge 91944-5

Modified:
    llvm/branches/Apple/Zoidberg/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=92059&r1=92058&r2=92059&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Dec 23 15:48:12 2009
@@ -2243,8 +2243,9 @@
         continue;
 
       // Figure out the value # from the RHS.
-      LHSValsDefinedFromRHS[VNI]=
-        RHS.getLiveRangeContaining(VNI->def.getPrevSlot())->valno;
+      LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
+      assert(lr && "Cannot find live range");
+      LHSValsDefinedFromRHS[VNI] = lr->valno;
     }
 
     // Loop over the value numbers of the RHS, seeing if any are defined from
@@ -2261,8 +2262,9 @@
         continue;
 
       // Figure out the value # from the LHS.
-      RHSValsDefinedFromLHS[VNI]=
-        LHS.getLiveRangeContaining(VNI->def.getPrevSlot())->valno;
+      LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
+      assert(lr && "Cannot find live range");
+      RHSValsDefinedFromLHS[VNI] = lr->valno;
     }
 
     LHSValNoAssignments.resize(LHS.getNumValNums(), -1);

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td?rev=92059&r1=92058&r2=92059&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td Wed Dec 23 15:48:12 2009
@@ -113,7 +113,7 @@
 def t_addrmode_sp : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
   let PrintMethod = "printThumbAddrModeSPOperand";
-  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
+  let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm);
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMRegisterInfo.td?rev=92059&r1=92058&r2=92059&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMRegisterInfo.td Wed Dec 23 15:48:12 2009
@@ -367,6 +367,19 @@
 // Condition code registers.
 def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
 
+// Just the stack pointer (for tSTRspi and friends).
+def JustSP : RegisterClass<"ARM", [i32], 32, [SP]> {
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+      JustSPClass::iterator
+      JustSPClass::allocation_order_end(const MachineFunction &MF) const {
+        return allocation_order_begin(MF);
+      }
+  }];
+}
+
 //===----------------------------------------------------------------------===//
 // Subregister Set Definitions... now that we have all of the pieces, define the
 // sub registers for each register.