[llvm-branch-commits] [llvm-branch] r79566 - in /llvm/branches/Apple/Leela: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vext.ll
Bill Wendling
isanbard at gmail.com
Thu Aug 20 14:08:34 PDT 2009
Author: void
Date: Thu Aug 20 16:08:34 2009
New Revision: 79566
URL: http://llvm.org/viewvc/llvm-project?rev=79566&view=rev
Log:
$ svn merge -c 79428 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r79428 into '.':
A test/CodeGen/ARM/vext.ll
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMISelLowering.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/ARM/vext.ll
- copied unchanged from r79428, llvm/trunk/test/CodeGen/ARM/vext.ll
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp?rev=79566&r1=79565&r2=79566&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 20 16:08:34 2009
@@ -487,6 +487,7 @@
case ARMISD::VST2D: return "ARMISD::VST2D";
case ARMISD::VST3D: return "ARMISD::VST3D";
case ARMISD::VST4D: return "ARMISD::VST4D";
+ case ARMISD::VEXT: return "ARMISD::VEXT";
case ARMISD::VREV64: return "ARMISD::VREV64";
case ARMISD::VREV32: return "ARMISD::VREV32";
case ARMISD::VREV16: return "ARMISD::VREV16";
@@ -2343,6 +2344,41 @@
SplatBitSize, DAG);
}
+static bool isVEXTMask(ShuffleVectorSDNode *N, bool &ReverseVEXT,
+ unsigned &Imm) {
+ EVT VT = N->getValueType(0);
+ unsigned NumElts = VT.getVectorNumElements();
+ ReverseVEXT = false;
+ Imm = N->getMaskElt(0);
+
+ // If this is a VEXT shuffle, the immediate value is the index of the first
+ // element. The other shuffle indices must be the successive elements after
+ // the first one.
+ unsigned ExpectedElt = Imm;
+ for (unsigned i = 1; i < NumElts; ++i) {
+
+ // Increment the expected index. If it wraps around, it may still be
+ // a VEXT but the source vectors must be swapped.
+ ExpectedElt += 1;
+ if (ExpectedElt == NumElts * 2) {
+ ExpectedElt = 0;
+ ReverseVEXT = true;
+ }
+
+ if (ExpectedElt != static_cast<unsigned>(N->getMaskElt(i)))
+ return false;
+ }
+
+ // Adjust the index value if the source operands will be swapped.
+ if (ReverseVEXT)
+ Imm -= NumElts;
+
+ // VEXT only handles 8-bit elements so scale the index for larger elements.
+ Imm *= VT.getVectorElementType().getSizeInBits() / 8;
+
+ return true;
+}
+
/// isVREVMask - Check if a vector shuffle corresponds to a VREV
/// instruction with the specified blocksize. (The order of the elements
/// within each block of the vector is reversed.)
@@ -2458,8 +2494,20 @@
return DAG.getNode(ARMISD::VDUP, dl, VT, Op0.getOperand(0));
}
return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0),
- DAG.getConstant(Lane, MVT::i32));
+ DAG.getConstant(Lane, MVT::i32));
}
+
+ bool ReverseVEXT;
+ unsigned Imm;
+ if (isVEXTMask(SVN, ReverseVEXT, Imm)) {
+ SDValue Op0 = SVN->getOperand(0);
+ SDValue Op1 = SVN->getOperand(1);
+ if (ReverseVEXT)
+ std::swap(Op0, Op1);
+ return DAG.getNode(ARMISD::VEXT, dl, VT, Op0, Op1,
+ DAG.getConstant(Imm, MVT::i32));
+ }
+
if (isVREVMask(SVN, 64))
return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
if (isVREVMask(SVN, 32))
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h?rev=79566&r1=79565&r2=79566&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.h Thu Aug 20 16:08:34 2009
@@ -128,6 +128,7 @@
VST4D,
// Vector shuffles:
+ VEXT, // extract
VREV64, // reverse elements within 64-bit doublewords
VREV32, // reverse elements within 32-bit words
VREV16 // reverse elements within 16-bit halfwords
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td?rev=79566&r1=79565&r2=79566&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td Thu Aug 20 16:08:34 2009
@@ -100,6 +100,10 @@
def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
[SDNPHasChain, SDNPMayStore]>;
+def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
+ SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
+def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
+
def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
@@ -1941,6 +1945,21 @@
def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
+// Other Vector Shuffles.
+
+// VEXT : Vector Extract
+
+def VEXTd : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
+ (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
+ "vext.8\t$dst, $lhs, $rhs, $index", "",
+ [(set DPR:$dst, (v8i8 (NEONvext (v8i8 DPR:$lhs),
+ (v8i8 DPR:$rhs), imm:$index)))]>;
+def VEXTq : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
+ (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
+ "vext.8\t$dst, $lhs, $rhs, $index", "",
+ [(set QPR:$dst, (v16i8 (NEONvext (v16i8 QPR:$lhs),
+ (v16i8 QPR:$rhs), imm:$index)))]>;
+
// VTRN : Vector Transpose
def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
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