[llvm-branch-commits] [llvm-branch] r79007 - in /llvm/branches/Apple/Leela: lib/Target/ARM/ARMConstantIslandPass.cpp lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Thumb2SizeReduction.cpp test/CodeGen/Thumb2/tls2.ll
Bill Wendling
isanbard at gmail.com
Fri Aug 14 10:58:13 PDT 2009
Author: void
Date: Fri Aug 14 12:58:13 2009
New Revision: 79007
URL: http://llvm.org/viewvc/llvm-project?rev=79007&view=rev
Log:
$ svn merge -c 78970 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r78970 into '.':
U test/CodeGen/Thumb2/tls2.ll
U lib/Target/ARM/ARMInstrThumb2.td
U lib/Target/ARM/ARMInstrThumb.td
U lib/Target/ARM/Thumb2SizeReduction.cpp
U lib/Target/ARM/ARMConstantIslandPass.cpp
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantIslandPass.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2SizeReduction.cpp
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/tls2.ll
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantIslandPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=79007&r1=79006&r2=79007&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantIslandPass.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMConstantIslandPass.cpp Fri Aug 14 12:58:13 2009
@@ -32,11 +32,12 @@
#include "llvm/ADT/Statistic.h"
using namespace llvm;
-STATISTIC(NumCPEs, "Number of constpool entries");
-STATISTIC(NumSplit, "Number of uncond branches inserted");
-STATISTIC(NumCBrFixed, "Number of cond branches fixed");
-STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
-STATISTIC(NumTBs, "Number of table branches generated");
+STATISTIC(NumCPEs, "Number of constpool entries");
+STATISTIC(NumSplit, "Number of uncond branches inserted");
+STATISTIC(NumCBrFixed, "Number of cond branches fixed");
+STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
+STATISTIC(NumTBs, "Number of table branches generated");
+STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
namespace {
/// ARMConstantIslands - Due to limited PC-relative displacements, ARM
@@ -179,6 +180,8 @@
bool FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br);
bool FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br);
bool UndoLRSpillRestore();
+ bool OptimizeThumb2Instructions(MachineFunction &MF);
+ bool OptimizeThumb2Branches(MachineFunction &MF);
bool OptimizeThumb2JumpTables(MachineFunction &MF);
unsigned GetOffsetOf(MachineInstr *MI) const;
@@ -292,8 +295,9 @@
MadeChange = true;
}
- // Let's see if we can use tbb / tbh to do jump tables.
- MadeChange |= OptimizeThumb2JumpTables(MF);
+ // Shrink 32-bit Thumb2 branch, load, and store instructions.
+ if (isThumb2)
+ MadeChange |= OptimizeThumb2Instructions(MF);
// After a while, this might be made debug-only, but it is not expensive.
verify(MF);
@@ -1077,7 +1081,7 @@
unsigned Size = CPEMI->getOperand(2).getImm();
MachineBasicBlock *NewMBB;
// Compute this only once, it's expensive. The 4 or 8 is the value the
- // hardware keeps in the PC (2 insns ahead of the reference).
+ // hardware keeps in the PC.
unsigned UserOffset = GetOffsetOf(UserMI) + (isThumb ? 4 : 8);
// See if the current entry is within range, or there is a clone of it
@@ -1350,6 +1354,62 @@
return MadeChange;
}
+bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
+ bool MadeChange = false;
+
+ // Shrink ADR and LDR from constantpool.
+ for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
+ CPUser &U = CPUsers[i];
+ unsigned Opcode = U.MI->getOpcode();
+ unsigned NewOpc = 0;
+ unsigned Scale = 1;
+ unsigned Bits = 0;
+ switch (Opcode) {
+ default: break;
+ case ARM::t2LEApcrel:
+ if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
+ NewOpc = ARM::tLEApcrel;
+ Bits = 8;
+ Scale = 4;
+ }
+ break;
+ case ARM::t2LDRpci:
+ if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
+ NewOpc = ARM::tLDRpci;
+ Bits = 8;
+ Scale = 4;
+ }
+ break;
+ }
+
+ if (!NewOpc)
+ continue;
+
+ unsigned UserOffset = GetOffsetOf(U.MI) + 4;
+ unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
+ // FIXME: Check if offset is multiple of scale if scale is not 4.
+ if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
+ U.MI->setDesc(TII->get(NewOpc));
+ MachineBasicBlock *MBB = U.MI->getParent();
+ BBSizes[MBB->getNumber()] -= 2;
+ AdjustBBOffsetsAfter(MBB, -2);
+ ++NumT2CPShrunk;
+ MadeChange = true;
+ }
+ }
+
+ MadeChange |= OptimizeThumb2JumpTables(MF);
+ MadeChange |= OptimizeThumb2Branches(MF);
+ return MadeChange;
+}
+
+bool ARMConstantIslands::OptimizeThumb2Branches(MachineFunction &MF) {
+ return false;
+}
+
+
+/// OptimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
+/// jumptables when it's possible.
bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
bool MadeChange = false;
@@ -1417,10 +1477,11 @@
if (!OptOk)
continue;
- // The previous instruction should be a t2LEApcrelJT, we want to delete
- // it as well.
+ // The previous instruction should be a tLEApcrel or t2LEApcrelJT, we want
+ // to delete it as well.
MachineInstr *LeaMI = --PrevI;
- if (LeaMI->getOpcode() != ARM::t2LEApcrelJT ||
+ if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
+ LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
LeaMI->getOperand(0).getReg() != BaseReg)
OptOk = false;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td?rev=79007&r1=79006&r2=79007&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb.td Fri Aug 14 12:58:13 2009
@@ -627,11 +627,12 @@
// tLEApcrel - Load a pc-relative address into a register without offending the
// assembler.
-def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
- "adr $dst, #$label", []>;
+def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALU,
+ "adr$p.n $dst, #$label", []>;
-def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id),
- IIC_iALU, "adr $dst, #${label}_${id}", []>;
+def tLEApcrelJT : T1I<(outs tGPR:$dst),
+ (ins i32imm:$label, lane_cst:$id, pred:$p),
+ IIC_iALU, "adr$p $dst, #${label}_${id}", []>;
//===----------------------------------------------------------------------===//
// TLS Instructions
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td?rev=79007&r1=79006&r2=79007&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td Fri Aug 14 12:58:13 2009
@@ -434,7 +434,6 @@
(ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALU,
"adr$p.w $dst, #${label}_${id}", []>;
-
// ADD r, sp, {so_imm|i12}
def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU,
"add", ".w $dst, $sp, $imm", []>;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=79007&r1=79006&r2=79007&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2SizeReduction.cpp Fri Aug 14 12:58:13 2009
@@ -71,6 +71,8 @@
{ ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 2,0, 0 },
{ ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 2,0, 0 },
{ ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
+ // FIXME: adr.n immediate offset must be multiple of 4.
+ //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0 },
{ ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
{ ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
{ ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/tls2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/tls2.ll?rev=79007&r1=79006&r2=79007&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/tls2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/tls2.ll Fri Aug 14 12:58:13 2009
@@ -1,7 +1,7 @@
; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \
; RUN: grep {i(gottpoff)}
; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi | \
-; RUN: grep {ldr.w r., \[pc, r.\]}
+; RUN: grep {ldr r., \[pc, r.\]}
; RUN: llvm-as < %s | llc -mtriple=thumbv7-linux-gnueabi \
; RUN: -relocation-model=pic | grep {__tls_get_addr}
More information about the llvm-branch-commits
mailing list