[llvm-branch-commits] [llvm-branch] r78901 - in /llvm/branches/Apple/Leela: lib/Target/ARM/Thumb1InstrInfo.cpp test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll

[Bill Wendling]

Author: void
Date: Thu Aug 13 03:13:37 2009
New Revision: 78901

URL: http://llvm.org/viewvc/llvm-project?rev=78901&view=rev
Log:
--- Merging r78893 into '.':
A    test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
U    lib/Target/ARM/Thumb1InstrInfo.cpp


Added:
    llvm/branches/Apple/Leela/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
      - copied unchanged from r78893, llvm/trunk/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll
Modified:
    llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp

Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=78901&r1=78900&r2=78901&view=diff

==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Aug 13 03:13:37 2009
@@ -91,12 +91,14 @@
   case ARM::tMOVgpr2gpr: {
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
-      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
+      if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
+          !isARMLowRegister(SrcReg))
         // tSpill cannot take a high register operand.
         return false;
     } else {          // move -> load
       unsigned DstReg = MI->getOperand(0).getReg();
-      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
+      if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
+          !isARMLowRegister(DstReg))
         // tRestore cannot target a high register operand.
         return false;
     }
@@ -114,7 +116,9 @@
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
+  assert((RC == ARM::tGPRRegisterClass ||
+          (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
+           isARMLowRegister(SrcReg))) && "Unknown regclass!");
 
   if (RC == ARM::tGPRRegisterClass) {
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
@@ -130,7 +134,9 @@
   DebugLoc DL = DebugLoc::getUnknownLoc();
   if (I != MBB.end()) DL = I->getDebugLoc();
 
-  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
+  assert((RC == ARM::tGPRRegisterClass ||
+          (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
+           isARMLowRegister(DestReg))) && "Unknown regclass!");
 
   if (RC == ARM::tGPRRegisterClass) {
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
@@ -212,7 +218,8 @@
     if (OpNum == 0) { // move -> store
       unsigned SrcReg = MI->getOperand(1).getReg();
       bool isKill = MI->getOperand(1).isKill();
-      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
+      if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
+          !isARMLowRegister(SrcReg))
         // tSpill cannot take a high register operand.
         break;
       NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
@@ -220,7 +227,8 @@
                              .addFrameIndex(FI).addImm(0));
     } else {          // move -> load
       unsigned DstReg = MI->getOperand(0).getReg();
-      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
+      if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
+          !isARMLowRegister(DstReg))
         // tRestore cannot target a high register operand.
         break;
       bool isDead = MI->getOperand(0).isDead();