<div dir="ltr">Hi Mohit,<br><br>It seems this revision broke compile step on lldb-x86_64-freebsd builder:<br><br>r 239995:<br><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_lldb-2Dx86-5F64-2Dfreebsd_builds_5871&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=XqvIlz1bZrePVb0CFWnTiCG-8YsTOXXKx1pNKElPqhs&e=">http://lab.llvm.org:8011/builders/lldb-x86_64-freebsd/builds/5871</a><br><br>r 239996:<br><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_lldb-2Dx86-5F64-2Dfreebsd_builds_5919&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=IYyUGi28rBWyi8XfEgsgMLxonzyY-07740YkWczWinY&e=">http://lab.llvm.org:8011/builders/lldb-x86_64-freebsd/builds/5919</a><br><br>Please have a look at this?<br><br>Thanks<br><br>Galina<br><div class="gmail_extra"><br><br><br><div class="gmail_quote">On Wed, Jun 17, 2015 at 11:03 PM, Mohit K. Bhakkad <span dir="ltr"><<a href="mailto:mohit.bhakkad@gmail.com" target="_blank">mohit.bhakkad@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: mohit.bhakkad<br>
Date: Thu Jun 18 01:03:27 2015<br>
New Revision: 239996<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D239996-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=-N6zsGZmwntaXWF9U6kzaed0g21JvgL6mplLB_-fXdw&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=239996&view=rev</a><br>
Log:<br>
[LLDB][MIPS] Emulation of MIPS64 floating-point branch instructions<br>
Patch by Jaydeep Patil<br>
<br>
SUMMARY:<br>
1. Added emulation of MIPS64 floating-point branch instructions<br>
2. Updated GetRegisterInfo to recognize floating-point registers<br>
3. Provided CPU information while creating createMCSubtargetInfo in disassembler<br>
4. Bug fix in emulation of JIC and JIALC<br>
5. Correct identification of breakpoint when set in a delay slot of a branch instruction<br>
<br>
Reviewers: clayborg<br>
Subscribers: bhushan, mohit.bhakkad, sagar, nitesh.jain, lldb-commits.<br>
Differential Revision: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D10355&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=RHvPMx_tftss1qjOGKyRA6uaKIfmXB9UTO8YTJs_Q5A&e=" rel="noreferrer" target="_blank">http://reviews.llvm.org/D10355</a><br>
<br>
Modified:<br>
    lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp<br>
    lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h<br>
    lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp<br>
    lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h<br>
<br>
Modified: lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_lldb_trunk_source_Plugins_Disassembler_llvm_DisassemblerLLVMC.cpp-3Frev-3D239996-26r1-3D239995-26r2-3D239996-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=nj6ioDCU1YEUEdFab8cybmEhYy641wnJmD-Usd9Dzh0&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp?rev=239996&r1=239995&r2=239996&view=diff</a><br>
==============================================================================<br>
--- lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp (original)<br>
+++ lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp Thu Jun 18 01:03:27 2015<br>
@@ -415,7 +415,7 @@ protected:<br>
<br>
<br>
<br>
-DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner):<br>
+DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner):<br>
     m_is_valid(true)<br>
 {<br>
     std::string Error;<br>
@@ -431,7 +431,7 @@ DisassemblerLLVMC::LLVMCDisassembler::LL<br>
<br>
     std::string features_str;<br>
<br>
-    m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, "",<br>
+    m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, cpu,<br>
                                                                 features_str));<br>
<br>
     std::unique_ptr<llvm::MCRegisterInfo> reg_info(curr_target->createMCRegInfo(triple));<br>
@@ -637,7 +637,45 @@ DisassemblerLLVMC::DisassemblerLLVMC (co<br>
         triple = thumb_arch.GetTriple().getTriple().c_str();<br>
     }<br>
<br>
-    m_disasm_ap.reset (new LLVMCDisassembler(triple, flavor, *this));<br>
+    const char *cpu = "";<br>
+<br>
+    switch (arch.GetCore())<br>
+    {<br>
+        case ArchSpec::eCore_mips32:<br>
+        case ArchSpec::eCore_mips32el:<br>
+            cpu = "mips32"; break;<br>
+        case ArchSpec::eCore_mips32r2:<br>
+        case ArchSpec::eCore_mips32r2el:<br>
+            cpu = "mips32r2"; break;<br>
+        case ArchSpec::eCore_mips32r3:<br>
+        case ArchSpec::eCore_mips32r3el:<br>
+            cpu = "mips32r3"; break;<br>
+        case ArchSpec::eCore_mips32r5:<br>
+        case ArchSpec::eCore_mips32r5el:<br>
+            cpu = "mips32r5"; break;<br>
+        case ArchSpec::eCore_mips32r6:<br>
+        case ArchSpec::eCore_mips32r6el:<br>
+            cpu = "mips32r6"; break;<br>
+        case ArchSpec::eCore_mips64:<br>
+        case ArchSpec::eCore_mips64el:<br>
+            cpu = "mips64"; break;<br>
+        case ArchSpec::eCore_mips64r2:<br>
+        case ArchSpec::eCore_mips64r2el:<br>
+            cpu = "mips64r2"; break;<br>
+        case ArchSpec::eCore_mips64r3:<br>
+        case ArchSpec::eCore_mips64r3el:<br>
+            cpu = "mips64r3"; break;<br>
+        case ArchSpec::eCore_mips64r5:<br>
+        case ArchSpec::eCore_mips64r5el:<br>
+            cpu = "mips64r5"; break;<br>
+        case ArchSpec::eCore_mips64r6:<br>
+        case ArchSpec::eCore_mips64r6el:<br>
+            cpu = "mips64r6"; break;<br>
+        default:<br>
+            cpu = ""; break;<br>
+    }<br>
+<br>
+    m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this));<br>
     if (!m_disasm_ap->IsValid())<br>
     {<br>
         // We use m_disasm_ap.get() to tell whether we are valid or not, so if this isn't good for some reason,<br>
@@ -649,7 +687,7 @@ DisassemblerLLVMC::DisassemblerLLVMC (co<br>
     if (arch.GetTriple().getArch() == llvm::Triple::arm)<br>
     {<br>
         std::string thumb_triple(thumb_arch.GetTriple().getTriple());<br>
-        m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), flavor, *this));<br>
+        m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), nullptr, flavor, *this));<br>
         if (!m_alternate_disasm_ap->IsValid())<br>
         {<br>
             m_disasm_ap.reset();<br>
<br>
Modified: lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_lldb_trunk_source_Plugins_Disassembler_llvm_DisassemblerLLVMC.h-3Frev-3D239996-26r1-3D239995-26r2-3D239996-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=0qxWtGWrWpcxOJrFSLunwT2BcqLvtPKBRU93pud1k00&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h?rev=239996&r1=239995&r2=239996&view=diff</a><br>
==============================================================================<br>
--- lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h (original)<br>
+++ lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h Thu Jun 18 01:03:27 2015<br>
@@ -41,7 +41,7 @@ class DisassemblerLLVMC : public lldb_pr<br>
     class LLVMCDisassembler<br>
     {<br>
     public:<br>
-        LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner);<br>
+        LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner);<br>
<br>
         ~LLVMCDisassembler();<br>
<br>
<br>
Modified: lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_lldb_trunk_source_Plugins_Instruction_MIPS64_EmulateInstructionMIPS64.cpp-3Frev-3D239996-26r1-3D239995-26r2-3D239996-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=qBpLFW7xW7n-MhchJsdeGVb5XG24vyIDxKS8Jk0g1Yc&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=239996&r1=239995&r2=239996&view=diff</a><br>
==============================================================================<br>
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp (original)<br>
+++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp Thu Jun 18 01:03:27 2015<br>
@@ -208,9 +208,41 @@ EmulateInstructionMIPS64::GetRegisterNam<br>
     {<br>
         switch (reg_num)<br>
         {<br>
-            case gcc_dwarf_sp_mips64: return "r29";<br>
+            case gcc_dwarf_sp_mips64:  return "r29";<br>
             case gcc_dwarf_r30_mips64: return "r30";<br>
-            case gcc_dwarf_ra_mips64: return "r31";<br>
+            case gcc_dwarf_ra_mips64:  return "r31";<br>
+            case gcc_dwarf_f0_mips64:  return "f0";<br>
+            case gcc_dwarf_f1_mips64:  return "f1";<br>
+            case gcc_dwarf_f2_mips64:  return "f2";<br>
+            case gcc_dwarf_f3_mips64:  return "f3";<br>
+            case gcc_dwarf_f4_mips64:  return "f4";<br>
+            case gcc_dwarf_f5_mips64:  return "f5";<br>
+            case gcc_dwarf_f6_mips64:  return "f6";<br>
+            case gcc_dwarf_f7_mips64:  return "f7";<br>
+            case gcc_dwarf_f8_mips64:  return "f8";<br>
+            case gcc_dwarf_f9_mips64:  return "f9";<br>
+            case gcc_dwarf_f10_mips64: return "f10";<br>
+            case gcc_dwarf_f11_mips64: return "f11";<br>
+            case gcc_dwarf_f12_mips64: return "f12";<br>
+            case gcc_dwarf_f13_mips64: return "f13";<br>
+            case gcc_dwarf_f14_mips64: return "f14";<br>
+            case gcc_dwarf_f15_mips64: return "f15";<br>
+            case gcc_dwarf_f16_mips64: return "f16";<br>
+            case gcc_dwarf_f17_mips64: return "f17";<br>
+            case gcc_dwarf_f18_mips64: return "f18";<br>
+            case gcc_dwarf_f19_mips64: return "f19";<br>
+            case gcc_dwarf_f20_mips64: return "f20";<br>
+            case gcc_dwarf_f21_mips64: return "f21";<br>
+            case gcc_dwarf_f22_mips64: return "f22";<br>
+            case gcc_dwarf_f23_mips64: return "f23";<br>
+            case gcc_dwarf_f24_mips64: return "f24";<br>
+            case gcc_dwarf_f25_mips64: return "f25";<br>
+            case gcc_dwarf_f26_mips64: return "f26";<br>
+            case gcc_dwarf_f27_mips64: return "f27";<br>
+            case gcc_dwarf_f28_mips64: return "f28";<br>
+            case gcc_dwarf_f29_mips64: return "f29";<br>
+            case gcc_dwarf_f30_mips64: return "f30";<br>
+            case gcc_dwarf_f31_mips64: return "f31";<br>
             default:<br>
                 break;<br>
         }<br>
@@ -257,7 +289,40 @@ EmulateInstructionMIPS64::GetRegisterNam<br>
         case gcc_dwarf_bad_mips64:      return "bad";<br>
         case gcc_dwarf_cause_mips64:    return "cause";<br>
         case gcc_dwarf_pc_mips64:       return "pc";<br>
-<br>
+        case gcc_dwarf_f0_mips64:       return "fp_reg[0]";<br>
+        case gcc_dwarf_f1_mips64:       return "fp_reg[1]";<br>
+        case gcc_dwarf_f2_mips64:       return "fp_reg[2]";<br>
+        case gcc_dwarf_f3_mips64:       return "fp_reg[3]";<br>
+        case gcc_dwarf_f4_mips64:       return "fp_reg[4]";<br>
+        case gcc_dwarf_f5_mips64:       return "fp_reg[5]";<br>
+        case gcc_dwarf_f6_mips64:       return "fp_reg[6]";<br>
+        case gcc_dwarf_f7_mips64:       return "fp_reg[7]";<br>
+        case gcc_dwarf_f8_mips64:       return "fp_reg[8]";<br>
+        case gcc_dwarf_f9_mips64:       return "fp_reg[9]";<br>
+        case gcc_dwarf_f10_mips64:      return "fp_reg[10]";<br>
+        case gcc_dwarf_f11_mips64:      return "fp_reg[11]";<br>
+        case gcc_dwarf_f12_mips64:      return "fp_reg[12]";<br>
+        case gcc_dwarf_f13_mips64:      return "fp_reg[13]";<br>
+        case gcc_dwarf_f14_mips64:      return "fp_reg[14]";<br>
+        case gcc_dwarf_f15_mips64:      return "fp_reg[15]";<br>
+        case gcc_dwarf_f16_mips64:      return "fp_reg[16]";<br>
+        case gcc_dwarf_f17_mips64:      return "fp_reg[17]";<br>
+        case gcc_dwarf_f18_mips64:      return "fp_reg[18]";<br>
+        case gcc_dwarf_f19_mips64:      return "fp_reg[19]";<br>
+        case gcc_dwarf_f20_mips64:      return "fp_reg[20]";<br>
+        case gcc_dwarf_f21_mips64:      return "fp_reg[21]";<br>
+        case gcc_dwarf_f22_mips64:      return "fp_reg[22]";<br>
+        case gcc_dwarf_f23_mips64:      return "fp_reg[23]";<br>
+        case gcc_dwarf_f24_mips64:      return "fp_reg[24]";<br>
+        case gcc_dwarf_f25_mips64:      return "fp_reg[25]";<br>
+        case gcc_dwarf_f26_mips64:      return "fp_reg[26]";<br>
+        case gcc_dwarf_f27_mips64:      return "fp_reg[27]";<br>
+        case gcc_dwarf_f28_mips64:      return "fp_reg[28]";<br>
+        case gcc_dwarf_f29_mips64:      return "fp_reg[29]";<br>
+        case gcc_dwarf_f30_mips64:      return "fp_reg[30]";<br>
+        case gcc_dwarf_f31_mips64:      return "fp_reg[31]";<br>
+        case gcc_dwarf_fcsr_mips64:     return "fcsr";<br>
+        case gcc_dwarf_fir_mips64:      return "fir";<br>
     }<br>
     return nullptr;<br>
 }<br>
@@ -284,13 +349,13 @@ EmulateInstructionMIPS64::GetRegisterInf<br>
        ::memset (&reg_info, 0, sizeof(RegisterInfo));<br>
        ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));<br>
<br>
-       if (reg_num == gcc_dwarf_sr_mips64)<br>
+       if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64)<br>
        {<br>
            reg_info.byte_size = 4;<br>
            reg_info.format = eFormatHex;<br>
            reg_info.encoding = eEncodingUint;<br>
        }<br>
-       else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_pc_mips64)<br>
+       else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_f31_mips64)<br>
        {<br>
            reg_info.byte_size = 8;<br>
            reg_info.format = eFormatHex;<br>
@@ -383,6 +448,16 @@ EmulateInstructionMIPS64::GetOpcodeForIn<br>
         { "JIC",        &EmulateInstructionMIPS64::Emulate_JIC,         "JIC rt,offset"             },<br>
         { "JR",         &EmulateInstructionMIPS64::Emulate_JR,          "JR target"                 },<br>
         { "JR_HB",      &EmulateInstructionMIPS64::Emulate_JR,          "JR.HB target"              },<br>
+        { "BC1F",       &EmulateInstructionMIPS64::Emulate_BC1F,        "BC1F cc, offset"           },<br>
+        { "BC1T",       &EmulateInstructionMIPS64::Emulate_BC1T,        "BC1T cc, offset"           },<br>
+        { "BC1FL",      &EmulateInstructionMIPS64::Emulate_BC1FL,       "BC1FL cc, offset"          },<br>
+        { "BC1TL",      &EmulateInstructionMIPS64::Emulate_BC1TL,       "BC1TL cc, offset"          },<br>
+        { "BC1EQZ",     &EmulateInstructionMIPS64::Emulate_BC1EQZ,      "BC1EQZ ft, offset"         },<br>
+        { "BC1NEZ",     &EmulateInstructionMIPS64::Emulate_BC1NEZ,      "BC1NEZ ft, offset"         },<br>
+        { "BC1ANY2F",   &EmulateInstructionMIPS64::Emulate_BC1ANY2F,    "BC1ANY2F cc, offset"       },<br>
+        { "BC1ANY2T",   &EmulateInstructionMIPS64::Emulate_BC1ANY2T,    "BC1ANY2T cc, offset"       },<br>
+        { "BC1ANY4F",   &EmulateInstructionMIPS64::Emulate_BC1ANY4F,    "BC1ANY4F cc, offset"       },<br>
+        { "BC1ANY4T",   &EmulateInstructionMIPS64::Emulate_BC1ANY4T,    "BC1ANY4T cc, offset"       },<br>
     };<br>
<br>
     static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);<br>
@@ -2347,7 +2422,7 @@ EmulateInstructionMIPS64::Emulate_JIALC<br>
      *      RA = PC + 4<br>
     */<br>
     rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
-    offset = insn.getOperand(0).getImm();<br>
+    offset = insn.getOperand(1).getImm();<br>
<br>
     pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
     if (!success)<br>
@@ -2383,7 +2458,7 @@ EmulateInstructionMIPS64::Emulate_JIC (l<br>
      *      PC = GPR[rt] + offset<br>
     */<br>
     rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
-    offset = insn.getOperand(0).getImm();<br>
+    offset = insn.getOperand(1).getImm();<br>
<br>
     rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success);<br>
     if (!success)<br>
@@ -2423,3 +2498,420 @@ EmulateInstructionMIPS64::Emulate_JR (ll<br>
<br>
     return true;<br>
 }<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1F cc, offset<br>
+     *  condition <- (FPConditionCode(cc) == 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    if ((fcsr & (1 << cc)) == 0)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1T cc, offset<br>
+     *  condition <- (FPConditionCode(cc) != 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    if ((fcsr & (1 << cc)) != 0)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1F cc, offset<br>
+     *  condition <- (FPConditionCode(cc) == 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    if ((fcsr & (1 << cc)) == 0)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 8;    /* skip delay slot */<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1T cc, offset<br>
+     *  condition <- (FPConditionCode(cc) != 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    if ((fcsr & (1 << cc)) != 0)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 8;    /* skip delay slot */<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t ft;<br>
+    uint64_t ft_val;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1EQZ ft, offset<br>
+     *  condition <- (FPR[ft].bit0 == 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + 4 + offset<br>
+    */<br>
+    ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    if ((ft_val & 1) == 0)<br>
+        target = pc + 4 + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t ft;<br>
+    uint64_t ft_val;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1NEZ ft, offset<br>
+     *  condition <- (FPR[ft].bit0 != 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + 4 + offset<br>
+    */<br>
+    ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    if ((ft_val & 1) != 0)<br>
+        target = pc + 4 + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1ANY2F cc, offset<br>
+     *  condition <- (FPConditionCode(cc) == 0<br>
+     *                  || FPConditionCode(cc+1) == 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    /* if any one bit is 0 */<br>
+    if (((fcsr >> cc) & 3) != 3)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1ANY2T cc, offset<br>
+     *  condition <- (FPConditionCode(cc) == 1<br>
+     *                  || FPConditionCode(cc+1) == 1)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    /* if any one bit is 1 */<br>
+    if (((fcsr >> cc) & 3) != 0)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1ANY4F cc, offset<br>
+     *  condition <- (FPConditionCode(cc) == 0<br>
+     *                  || FPConditionCode(cc+1) == 0)<br>
+     *                  || FPConditionCode(cc+2) == 0)<br>
+     *                  || FPConditionCode(cc+3) == 0)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    /* if any one bit is 0 */<br>
+    if (((fcsr >> cc) & 0xf) != 0xf)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
+}<br>
+<br>
+bool<br>
+EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn)<br>
+{<br>
+    bool success = false;<br>
+    uint32_t cc, fcsr;<br>
+    int64_t target, pc, offset;<br>
+<br>
+    /*<br>
+     * BC1ANY4T cc, offset<br>
+     *  condition <- (FPConditionCode(cc) == 1<br>
+     *                  || FPConditionCode(cc+1) == 1)<br>
+     *                  || FPConditionCode(cc+2) == 1)<br>
+     *                  || FPConditionCode(cc+3) == 1)<br>
+     *      if condition then<br>
+     *          offset = sign_ext (offset)<br>
+     *          PC = PC + offset<br>
+    */<br>
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());<br>
+    offset = insn.getOperand(1).getImm();<br>
+<br>
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);<br>
+    if (!success)<br>
+        return false;<br>
+<br>
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */<br>
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);<br>
+<br>
+    /* if any one bit is 1 */<br>
+    if (((fcsr >> cc) & 0xf) != 0)<br>
+        target = pc + offset;<br>
+    else<br>
+        target = pc + 4;<br>
+<br>
+    Context context;<br>
+<br>
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))<br>
+        return false;<br>
+<br>
+    return true;<br>
<br>
Modified: lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_lldb_trunk_source_Plugins_Instruction_MIPS64_EmulateInstructionMIPS64.h-3Frev-3D239996-26r1-3D239995-26r2-3D239996-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=MEqT8U_n7oNfuDW5NRbY3ZV384ZquXIYFPWmprwUdKM&m=KdH1dPm1yXHqsU3uvYBozkbpWik5MovrgZXByyH6ZnM&s=OyZJR5yZ43u7rKsmGFtuSLv6ripo8Bs787i9-3ExvhU&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h?rev=239996&r1=239995&r2=239996&view=diff</a><br>
==============================================================================<br>
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h (original)<br>
+++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h Thu Jun 18 01:03:27 2015<br>
@@ -266,6 +266,36 @@ protected:<br>
     Emulate_JR (llvm::MCInst& insn);<br>
<br>
     bool<br>
+    Emulate_BC1F (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1T (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1FL (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1TL (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1EQZ (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1NEZ (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1ANY2F  (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1ANY2T  (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1ANY4F  (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
+    Emulate_BC1ANY4T  (llvm::MCInst& insn);<br>
+<br>
+    bool<br>
     nonvolatile_reg_p (uint64_t regnum);<br>
<br>
     const char *<br>
<br>
<br>
_______________________________________________<br>
lldb-commits mailing list<br>
<a href="mailto:lldb-commits@cs.uiuc.edu">lldb-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits" rel="noreferrer" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits</a><br>
</blockquote></div><br></div></div>