[Lldb-commits] [lldb] 2b8db38 - [lldb] Move register info "augmentation" from gdb-remote into ABI
Pavel Labath via lldb-commits
lldb-commits at lists.llvm.org
Tue Dec 3 02:41:38 PST 2019
Author: Pavel Labath
Date: 2019-12-03T11:39:20+01:00
New Revision: 2b8db387f2a616f39a077ede18c6366f2ea9f203
URL: https://github.com/llvm/llvm-project/commit/2b8db387f2a616f39a077ede18c6366f2ea9f203
DIFF: https://github.com/llvm/llvm-project/commit/2b8db387f2a616f39a077ede18c6366f2ea9f203.diff
LOG: [lldb] Move register info "augmentation" from gdb-remote into ABI
Summary:
Previously the ABI plugin exposed some "register infos" and the
gdb-remote code used those to fill in the missing bits. Now, the
"filling in" code is in the ABI plugin itself, and the gdb-remote code
just invokes that.
The motivation for this is two-fold:
a) the "augmentation" logic is useful outside of process gdb-remote. For
instance, it would allow us to avoid repeating the register number
definitions in minidump code.
b) It gives more implementation freedom to the ABI classes. Now that
these "register infos" are essentially implementation details, classes
can use other methods to obtain dwarf/eh_frame register numbers -- for
instance they can consult llvm MC layer.
Since the augmentation code was not currently tested anywhere, I took
the opportunity to create a simple test for it.
Reviewers: jasonmolenda, clayborg, tatyana-krasnukha
Subscribers: aprantl, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D70906
Added:
lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/basic_eh_frame.yaml
Modified:
lldb/include/lldb/Target/ABI.h
lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestTargetXMLArch.py
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
lldb/source/Target/ABI.cpp
Removed:
################################################################################
diff --git a/lldb/include/lldb/Target/ABI.h b/lldb/include/lldb/Target/ABI.h
index 93378abc2ac2..1aff1e2f7817 100644
--- a/lldb/include/lldb/Target/ABI.h
+++ b/lldb/include/lldb/Target/ABI.h
@@ -126,12 +126,7 @@ class ABI : public PluginInterface {
llvm::MCRegisterInfo &GetMCRegisterInfo() { return *m_mc_register_info_up; }
- virtual const RegisterInfo *GetRegisterInfoArray(uint32_t &count) = 0;
-
- bool GetRegisterInfoByName(ConstString name, RegisterInfo &info);
-
- bool GetRegisterInfoByKind(lldb::RegisterKind reg_kind, uint32_t reg_num,
- RegisterInfo &info);
+ virtual void AugmentRegisterInfo(RegisterInfo &info);
virtual bool GetPointerReturnRegister(const char *&name) { return false; }
@@ -143,6 +138,10 @@ class ABI : public PluginInterface {
assert(m_mc_register_info_up && "ABI must have MCRegisterInfo");
}
+ bool GetRegisterInfoByName(ConstString name, RegisterInfo &info);
+
+ virtual const RegisterInfo *GetRegisterInfoArray(uint32_t &count) = 0;
+
/// Utility function to construct a MCRegisterInfo using the ArchSpec triple.
/// Plugins wishing to customize the construction can construct the
/// MCRegisterInfo themselves.
diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestTargetXMLArch.py b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestTargetXMLArch.py
index 9ea7cc8a4c7e..20e575ae978b 100644
--- a/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestTargetXMLArch.py
+++ b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/TestTargetXMLArch.py
@@ -4,6 +4,101 @@
from lldbsuite.test.decorators import *
from gdbclientutils import *
+class MyResponder(MockGDBServerResponder):
+ def qXferRead(self, obj, annex, offset, length):
+ if annex == "target.xml":
+ return """<?xml version="1.0"?>
+ <target version="1.0">
+ <architecture>i386:x86-64</architecture>
+ <feature name="org.gnu.gdb.i386.core">
+
+ <flags id="i386_eflags" size="4">
+ <field name="CF" start="0" end="0"/>
+ <field name="" start="1" end="1"/>
+ <field name="PF" start="2" end="2"/>
+ <field name="AF" start="4" end="4"/>
+ <field name="ZF" start="6" end="6"/>
+ <field name="SF" start="7" end="7"/>
+ <field name="TF" start="8" end="8"/>
+ <field name="IF" start="9" end="9"/>
+ <field name="DF" start="10" end="10"/>
+ <field name="OF" start="11" end="11"/>
+ <field name="NT" start="14" end="14"/>
+ <field name="RF" start="16" end="16"/>
+ <field name="VM" start="17" end="17"/>
+ <field name="AC" start="18" end="18"/>
+ <field name="VIF" start="19" end="19"/>
+ <field name="VIP" start="20" end="20"/>
+ <field name="ID" start="21" end="21"/>
+ </flags>
+
+ <reg name="rax" bitsize="64" regnum="0" type="int" group="general"/>
+ <reg name="rbx" bitsize="64" regnum="1" type="int" group="general"/>
+ <reg name="rcx" bitsize="64" regnum="2" type="int" group="general"/>
+ <reg name="rdx" bitsize="64" regnum="3" type="int" group="general"/>
+ <reg name="rsi" bitsize="64" regnum="4" type="int" group="general"/>
+ <reg name="rdi" bitsize="64" regnum="5" type="int" group="general"/>
+ <reg name="rbp" bitsize="64" regnum="6" type="data_ptr" group="general"/>
+ <reg name="rsp" bitsize="64" regnum="7" type="data_ptr" group="general"/>
+ <reg name="r8" bitsize="64" regnum="8" type="int" group="general"/>
+ <reg name="r9" bitsize="64" regnum="9" type="int" group="general"/>
+ <reg name="r10" bitsize="64" regnum="10" type="int" group="general"/>
+ <reg name="r11" bitsize="64" regnum="11" type="int" group="general"/>
+ <reg name="r12" bitsize="64" regnum="12" type="int" group="general"/>
+ <reg name="r13" bitsize="64" regnum="13" type="int" group="general"/>
+ <reg name="r14" bitsize="64" regnum="14" type="int" group="general"/>
+ <reg name="r15" bitsize="64" regnum="15" type="int" group="general"/>
+ <reg name="rip" bitsize="64" regnum="16" type="code_ptr" group="general"/>
+ <reg name="eflags" bitsize="32" regnum="17" type="i386_eflags" group="general"/>
+
+ <reg name="cs" bitsize="32" regnum="18" type="int" group="general"/>
+ <reg name="ss" bitsize="32" regnum="19" type="int" group="general"/>
+ <reg name="ds" bitsize="32" regnum="20" type="int" group="general"/>
+ <reg name="es" bitsize="32" regnum="21" type="int" group="general"/>
+ <reg name="fs" bitsize="32" regnum="22" type="int" group="general"/>
+ <reg name="gs" bitsize="32" regnum="23" type="int" group="general"/>
+
+ <reg name="st0" bitsize="80" regnum="24" type="i387_ext" group="float"/>
+ <reg name="st1" bitsize="80" regnum="25" type="i387_ext" group="float"/>
+ <reg name="st2" bitsize="80" regnum="26" type="i387_ext" group="float"/>
+ <reg name="st3" bitsize="80" regnum="27" type="i387_ext" group="float"/>
+ <reg name="st4" bitsize="80" regnum="28" type="i387_ext" group="float"/>
+ <reg name="st5" bitsize="80" regnum="29" type="i387_ext" group="float"/>
+ <reg name="st6" bitsize="80" regnum="30" type="i387_ext" group="float"/>
+ <reg name="st7" bitsize="80" regnum="31" type="i387_ext" group="float"/>
+
+ <reg name="fctrl" bitsize="32" regnum="32" type="int" group="float"/>
+ <reg name="fstat" bitsize="32" regnum="33" type="int" group="float"/>
+ <reg name="ftag" bitsize="32" regnum="34" type="int" group="float"/>
+ <reg name="fiseg" bitsize="32" regnum="35" type="int" group="float"/>
+ <reg name="fioff" bitsize="32" regnum="36" type="int" group="float"/>
+ <reg name="foseg" bitsize="32" regnum="37" type="int" group="float"/>
+ <reg name="fooff" bitsize="32" regnum="38" type="int" group="float"/>
+ <reg name="fop" bitsize="32" regnum="39" type="int" group="float"/>
+ </feature>
+ </target>""", False
+ else:
+ return None, False
+
+ def qC(self):
+ return "QC1"
+
+ def haltReason(self):
+ return "T05thread:00000001;06:9038d60f00700000;07:98b4062680ffffff;10:c0d7bf1b80ffffff;"
+
+ def readRegister(self, register):
+ regs = {0x0: "00b0060000610000",
+ 0xa: "68fe471c80ffffff",
+ 0xc: "60574a1c80ffffff",
+ 0xd: "18f3042680ffffff",
+ 0xe: "be8a4d7142000000",
+ 0xf: "50df471c80ffffff",
+ 0x10: "c0d7bf1b80ffffff" }
+ if register in regs:
+ return regs[register]
+ else:
+ return "0000000000000000"
+
class TestTargetXMLArch(GDBRemoteTestBase):
@skipIfXmlSupportMissing
@@ -14,102 +109,6 @@ def test(self):
Test lldb's parsing of the <architecture> tag in the target.xml register
description packet.
"""
- class MyResponder(MockGDBServerResponder):
-
- def qXferRead(self, obj, annex, offset, length):
- if annex == "target.xml":
- return """<?xml version="1.0"?>
- <target version="1.0">
- <architecture>i386:x86-64</architecture>
- <feature name="org.gnu.gdb.i386.core">
-
- <flags id="i386_eflags" size="4">
- <field name="CF" start="0" end="0"/>
- <field name="" start="1" end="1"/>
- <field name="PF" start="2" end="2"/>
- <field name="AF" start="4" end="4"/>
- <field name="ZF" start="6" end="6"/>
- <field name="SF" start="7" end="7"/>
- <field name="TF" start="8" end="8"/>
- <field name="IF" start="9" end="9"/>
- <field name="DF" start="10" end="10"/>
- <field name="OF" start="11" end="11"/>
- <field name="NT" start="14" end="14"/>
- <field name="RF" start="16" end="16"/>
- <field name="VM" start="17" end="17"/>
- <field name="AC" start="18" end="18"/>
- <field name="VIF" start="19" end="19"/>
- <field name="VIP" start="20" end="20"/>
- <field name="ID" start="21" end="21"/>
- </flags>
-
- <reg name="rax" bitsize="64" regnum="0" type="int" group="general"/>
- <reg name="rbx" bitsize="64" regnum="1" type="int" group="general"/>
- <reg name="rcx" bitsize="64" regnum="2" type="int" group="general"/>
- <reg name="rdx" bitsize="64" regnum="3" type="int" group="general"/>
- <reg name="rsi" bitsize="64" regnum="4" type="int" group="general"/>
- <reg name="rdi" bitsize="64" regnum="5" type="int" group="general"/>
- <reg name="rbp" bitsize="64" regnum="6" type="data_ptr" group="general"/>
- <reg name="rsp" bitsize="64" regnum="7" type="data_ptr" group="general"/>
- <reg name="r8" bitsize="64" regnum="8" type="int" group="general"/>
- <reg name="r9" bitsize="64" regnum="9" type="int" group="general"/>
- <reg name="r10" bitsize="64" regnum="10" type="int" group="general"/>
- <reg name="r11" bitsize="64" regnum="11" type="int" group="general"/>
- <reg name="r12" bitsize="64" regnum="12" type="int" group="general"/>
- <reg name="r13" bitsize="64" regnum="13" type="int" group="general"/>
- <reg name="r14" bitsize="64" regnum="14" type="int" group="general"/>
- <reg name="r15" bitsize="64" regnum="15" type="int" group="general"/>
- <reg name="rip" bitsize="64" regnum="16" type="code_ptr" group="general"/>
- <reg name="eflags" bitsize="32" regnum="17" type="i386_eflags" group="general"/>
-
- <reg name="cs" bitsize="32" regnum="18" type="int" group="general"/>
- <reg name="ss" bitsize="32" regnum="19" type="int" group="general"/>
- <reg name="ds" bitsize="32" regnum="20" type="int" group="general"/>
- <reg name="es" bitsize="32" regnum="21" type="int" group="general"/>
- <reg name="fs" bitsize="32" regnum="22" type="int" group="general"/>
- <reg name="gs" bitsize="32" regnum="23" type="int" group="general"/>
-
- <reg name="st0" bitsize="80" regnum="24" type="i387_ext" group="float"/>
- <reg name="st1" bitsize="80" regnum="25" type="i387_ext" group="float"/>
- <reg name="st2" bitsize="80" regnum="26" type="i387_ext" group="float"/>
- <reg name="st3" bitsize="80" regnum="27" type="i387_ext" group="float"/>
- <reg name="st4" bitsize="80" regnum="28" type="i387_ext" group="float"/>
- <reg name="st5" bitsize="80" regnum="29" type="i387_ext" group="float"/>
- <reg name="st6" bitsize="80" regnum="30" type="i387_ext" group="float"/>
- <reg name="st7" bitsize="80" regnum="31" type="i387_ext" group="float"/>
-
- <reg name="fctrl" bitsize="32" regnum="32" type="int" group="float"/>
- <reg name="fstat" bitsize="32" regnum="33" type="int" group="float"/>
- <reg name="ftag" bitsize="32" regnum="34" type="int" group="float"/>
- <reg name="fiseg" bitsize="32" regnum="35" type="int" group="float"/>
- <reg name="fioff" bitsize="32" regnum="36" type="int" group="float"/>
- <reg name="foseg" bitsize="32" regnum="37" type="int" group="float"/>
- <reg name="fooff" bitsize="32" regnum="38" type="int" group="float"/>
- <reg name="fop" bitsize="32" regnum="39" type="int" group="float"/>
- </feature>
- </target>""", False
- else:
- return None, False
-
- def qC(self):
- return "QC1"
-
- def haltReason(self):
- return "T05thread:00000001;06:9038d60f00700000;07:98b4062680ffffff;10:c0d7bf1b80ffffff;"
-
- def readRegister(self, register):
- regs = {0x0: "00b0060000610000",
- 0xa: "68fe471c80ffffff",
- 0xc: "60574a1c80ffffff",
- 0xd: "18f3042680ffffff",
- 0xe: "be8a4d7142000000",
- 0xf: "50df471c80ffffff",
- 0x10: "c0d7bf1b80ffffff" }
- if register in regs:
- return regs[register]
- else:
- return "0000000000000000"
-
self.server.responder = MyResponder()
interp = self.dbg.GetCommandInterpreter()
result = lldb.SBCommandReturnObject()
@@ -125,3 +124,22 @@ def readRegister(self, register):
interp.HandleCommand("target list", result)
print(result.GetOutput())
self.assertTrue(target.GetTriple().startswith('x86_64-unknown-unknown'))
+
+ @skipIfXmlSupportMissing
+ @skipIfRemote
+ def test_register_augmentation(self):
+ """
+ Test that we correctly associate the register info with the eh_frame
+ register numbers.
+ """
+
+ target = self.createTarget("basic_eh_frame.yaml")
+ self.server.responder = MyResponder()
+
+ process = self.connect(target)
+ lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
+ [lldb.eStateStopped])
+ self.filecheck("image show-unwind -n foo", __file__,
+ "--check-prefix=UNWIND")
+# UNWIND: eh_frame UnwindPlan:
+# UNWIND: row[0]: 0: CFA=rsp+128 => rip=[CFA-8]
diff --git a/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/basic_eh_frame.yaml b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/basic_eh_frame.yaml
new file mode 100644
index 000000000000..384b9b992b40
--- /dev/null
+++ b/lldb/packages/Python/lldbsuite/test/functionalities/gdb_remote_client/basic_eh_frame.yaml
@@ -0,0 +1,48 @@
+--- !ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ Type: ET_EXEC
+ Machine: EM_X86_64
+ Entry: 0x0000000000401000
+Sections:
+ - Name: .text
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
+ Address: 0x0000000000401000
+ AddressAlign: 0x0000000000000001
+ Content: C3
+ - Name: .eh_frame
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC ]
+ Address: 0x0000000000402000
+ AddressAlign: 0x0000000000000008
+ Content: 1800000000000000017A5200017810011B0C070890010E80010000001000000020000000DCEFFFFF0100000000000000
+Symbols:
+ - Name: .text
+ Type: STT_SECTION
+ Section: .text
+ Value: 0x0000000000401000
+ - Name: .eh_frame
+ Type: STT_SECTION
+ Section: .eh_frame
+ Value: 0x0000000000402000
+ - Name: _start
+ Binding: STB_GLOBAL
+ - Name: __bss_start
+ Section: .eh_frame
+ Binding: STB_GLOBAL
+ Value: 0x0000000000404000
+ - Name: foo
+ Section: .text
+ Binding: STB_GLOBAL
+ Value: 0x0000000000401000
+ - Name: _edata
+ Section: .eh_frame
+ Binding: STB_GLOBAL
+ Value: 0x0000000000404000
+ - Name: _end
+ Section: .eh_frame
+ Binding: STB_GLOBAL
+ Value: 0x0000000000404000
+...
diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
index 5d1dd79c2ffa..dfef06aa6eaf 100644
--- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -388,36 +388,6 @@ bool ProcessGDBRemote::ParsePythonTargetDefinition(
return false;
}
-// If the remote stub didn't give us eh_frame or DWARF register numbers for a
-// register, see if the ABI can provide them.
-// DWARF and eh_frame register numbers are defined as a part of the ABI.
-static void AugmentRegisterInfoViaABI(RegisterInfo ®_info,
- ConstString reg_name, ABISP abi_sp) {
- if (reg_info.kinds[eRegisterKindEHFrame] == LLDB_INVALID_REGNUM ||
- reg_info.kinds[eRegisterKindDWARF] == LLDB_INVALID_REGNUM) {
- if (abi_sp) {
- RegisterInfo abi_reg_info;
- if (abi_sp->GetRegisterInfoByName(reg_name, abi_reg_info)) {
- if (reg_info.kinds[eRegisterKindEHFrame] == LLDB_INVALID_REGNUM &&
- abi_reg_info.kinds[eRegisterKindEHFrame] != LLDB_INVALID_REGNUM) {
- reg_info.kinds[eRegisterKindEHFrame] =
- abi_reg_info.kinds[eRegisterKindEHFrame];
- }
- if (reg_info.kinds[eRegisterKindDWARF] == LLDB_INVALID_REGNUM &&
- abi_reg_info.kinds[eRegisterKindDWARF] != LLDB_INVALID_REGNUM) {
- reg_info.kinds[eRegisterKindDWARF] =
- abi_reg_info.kinds[eRegisterKindDWARF];
- }
- if (reg_info.kinds[eRegisterKindGeneric] == LLDB_INVALID_REGNUM &&
- abi_reg_info.kinds[eRegisterKindGeneric] != LLDB_INVALID_REGNUM) {
- reg_info.kinds[eRegisterKindGeneric] =
- abi_reg_info.kinds[eRegisterKindGeneric];
- }
- }
- }
- }
-}
-
static size_t SplitCommaSeparatedRegisterNumberString(
const llvm::StringRef &comma_separated_regiter_numbers,
std::vector<uint32_t> ®nums, int base) {
@@ -615,12 +585,12 @@ void ProcessGDBRemote::BuildDynamicRegisterInfo(bool force) {
reg_info.invalidate_regs = invalidate_regs.data();
}
+ reg_info.name = reg_name.AsCString();
// We have to make a temporary ABI here, and not use the GetABI because
// this code gets called in DidAttach, when the target architecture
// (and consequently the ABI we'll get from the process) may be wrong.
- ABISP abi_to_use = ABI::FindPlugin(shared_from_this(), arch_to_use);
-
- AugmentRegisterInfoViaABI(reg_info, reg_name, abi_to_use);
+ if (ABISP abi_sp = ABI::FindPlugin(shared_from_this(), arch_to_use))
+ abi_sp->AugmentRegisterInfo(reg_info);
m_register_info.AddRegister(reg_info, reg_name, alt_name, set_name);
} else {
@@ -4483,7 +4453,9 @@ bool ParseRegisters(XMLNode feature_node, GdbServerTargetInfo &target_info,
}
++cur_reg_num;
- AugmentRegisterInfoViaABI(reg_info, reg_name, abi_sp);
+ reg_info.name = reg_name.AsCString();
+ if (abi_sp)
+ abi_sp->AugmentRegisterInfo(reg_info);
dyn_reg_info.AddRegister(reg_info, reg_name, alt_name, set_name);
return true; // Keep iterating through all "reg" elements
diff --git a/lldb/source/Target/ABI.cpp b/lldb/source/Target/ABI.cpp
index 005261e0ddee..6217ee2ed9ce 100644
--- a/lldb/source/Target/ABI.cpp
+++ b/lldb/source/Target/ABI.cpp
@@ -63,24 +63,6 @@ bool ABI::GetRegisterInfoByName(ConstString name, RegisterInfo &info) {
return false;
}
-bool ABI::GetRegisterInfoByKind(RegisterKind reg_kind, uint32_t reg_num,
- RegisterInfo &info) {
- if (reg_kind < eRegisterKindEHFrame || reg_kind >= kNumRegisterKinds)
- return false;
-
- uint32_t count = 0;
- const RegisterInfo *register_info_array = GetRegisterInfoArray(count);
- if (register_info_array) {
- for (uint32_t i = 0; i < count; ++i) {
- if (register_info_array[i].kinds[reg_kind] == reg_num) {
- info = register_info_array[i];
- return true;
- }
- }
- }
- return false;
-}
-
ValueObjectSP ABI::GetReturnValueObject(Thread &thread, CompilerType &ast_type,
bool persistent) const {
if (!ast_type.IsValid())
@@ -229,3 +211,20 @@ std::unique_ptr<llvm::MCRegisterInfo> ABI::MakeMCRegisterInfo(const ArchSpec &ar
assert(info_up);
return info_up;
}
+
+void ABI::AugmentRegisterInfo(RegisterInfo &info) {
+ if (info.kinds[eRegisterKindEHFrame] != LLDB_INVALID_REGNUM &&
+ info.kinds[eRegisterKindDWARF] != LLDB_INVALID_REGNUM)
+ return;
+
+ RegisterInfo abi_info;
+ if (!GetRegisterInfoByName(ConstString(info.name), abi_info))
+ return;
+
+ if (info.kinds[eRegisterKindEHFrame] == LLDB_INVALID_REGNUM)
+ info.kinds[eRegisterKindEHFrame] = abi_info.kinds[eRegisterKindEHFrame];
+ if (info.kinds[eRegisterKindDWARF] == LLDB_INVALID_REGNUM)
+ info.kinds[eRegisterKindDWARF] = abi_info.kinds[eRegisterKindDWARF];
+ if (info.kinds[eRegisterKindGeneric] == LLDB_INVALID_REGNUM)
+ info.kinds[eRegisterKindGeneric] = abi_info.kinds[eRegisterKindGeneric];
+}
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