[Lldb-commits] [lldb] r364481 - Use the // integer divide operator in these

[Davide Italiano via lldb-commits]

Thank you Jason!


On Wed, Jun 26, 2019 at 2:41 PM Jason Molenda via lldb-commits
<lldb-commits at lists.llvm.org> wrote:
>
> Author: jmolenda
> Date: Wed Jun 26 14:41:07 2019
> New Revision: 364481
>
> URL: http://llvm.org/viewvc/llvm-project?rev=364481&view=rev
> Log:
> Use the // integer divide operator in these
> target definition files, like Davide's change to x86_64_target_definition.py.
>
> Modified:
>     lldb/trunk/examples/python/x86_64_linux_target_definition.py
>     lldb/trunk/examples/python/x86_64_qemu_target_definition.py
>
> Modified: lldb/trunk/examples/python/x86_64_linux_target_definition.py
> URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/examples/python/x86_64_linux_target_definition.py?rev=364481&r1=364480&r2=364481&view=diff
> ==============================================================================
> --- lldb/trunk/examples/python/x86_64_linux_target_definition.py (original)
> +++ lldb/trunk/examples/python/x86_64_linux_target_definition.py Wed Jun 26 14:41:07 2019
> @@ -740,7 +740,7 @@ def get_target_definition():
>              # info
>              if 'slice' not in reg_info and 'composite' not in reg_info:
>                  reg_info['offset'] = offset
> -                offset += reg_info['bitsize'] / 8
> +                offset += reg_info['bitsize'] // 8
>
>              # Set the GCC/DWARF register number for this register if it has one
>              reg_num = get_reg_num(name_to_gcc_dwarf_regnum, reg_name)
>
> Modified: lldb/trunk/examples/python/x86_64_qemu_target_definition.py
> URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/examples/python/x86_64_qemu_target_definition.py?rev=364481&r1=364480&r2=364481&view=diff
> ==============================================================================
> --- lldb/trunk/examples/python/x86_64_qemu_target_definition.py (original)
> +++ lldb/trunk/examples/python/x86_64_qemu_target_definition.py Wed Jun 26 14:41:07 2019
> @@ -738,7 +738,7 @@ def get_target_definition():
>              # info
>              if 'slice' not in reg_info and 'composite' not in reg_info:
>                  reg_info['offset'] = offset
> -                offset += reg_info['bitsize'] / 8
> +                offset += reg_info['bitsize'] // 8
>
>              # Set the GCC/DWARF register number for this register if it has one
>              reg_num = get_reg_num(name_to_gcc_dwarf_regnum, reg_name)
>
>
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