[Lldb-commits] [PATCH] lldb - towards AArch64 being recognised as platform architecture

[Greg Clayton]

Looks good.

> On Jul 13, 2014, at 9:59 AM, Paul Osmialowski <pawelo at king.net.pl> wrote:
> 
> New improved version posted.
> 
> http://reviews.llvm.org/D4381
> 
> Files:
>  include/lldb/Core/ArchSpec.h
>  source/Core/ArchSpec.cpp
> 
> Index: include/lldb/Core/ArchSpec.h
> ===================================================================
> --- include/lldb/Core/ArchSpec.h
> +++ include/lldb/Core/ArchSpec.h
> @@ -64,6 +64,8 @@
>         eCore_thumbv7m,
>         eCore_thumbv7em,
>         eCore_arm_arm64,
> +        eCore_arm_armv8,
> +        eCore_arm_aarch64,
> 
>         eCore_mips64,
> 
> Index: source/Core/ArchSpec.cpp
> ===================================================================
> --- source/Core/ArchSpec.cpp
> +++ source/Core/ArchSpec.cpp
> @@ -78,6 +78,8 @@
>     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7m        , "thumbv7m"  },
>     { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7em       , "thumbv7em" },
>     { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64  , ArchSpec::eCore_arm_arm64       , "arm64"     },
> +    { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64  , ArchSpec::eCore_arm_armv8       , "armv8"     },
> +    { eByteOrderLittle, 8, 4, 4, llvm::Triple::arm64  , ArchSpec::eCore_arm_aarch64     , "aarch64"   },
> 
>     { eByteOrderBig   , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64          , "mips64"    },
> 
> @@ -248,6 +250,7 @@
>     { ArchSpec::eCore_ppc_generic     , llvm::ELF::EM_PPC    , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
>     { ArchSpec::eCore_ppc64_generic   , llvm::ELF::EM_PPC64  , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
>     { ArchSpec::eCore_arm_generic     , llvm::ELF::EM_ARM    , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
> +    { ArchSpec::eCore_arm_aarch64     , llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM64
>     { ArchSpec::eCore_sparc9_generic  , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
>     { ArchSpec::eCore_x86_64_x86_64   , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
>     { ArchSpec::eCore_mips64          , llvm::ELF::EM_MIPS   , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
> @@ -963,6 +966,39 @@
>         }
>         break;
> 
> +    case ArchSpec::eCore_arm_armv8:
> +        if (!enforce_exact_match)
> +        {
> +            if (core2 == ArchSpec::eCore_arm_arm64)
> +                return true;
> +            if (core2 == ArchSpec::eCore_arm_aarch64)
> +                return true;
> +            try_inverse = false;
> +        }
> +        break;
> +
> +    case ArchSpec::eCore_arm_aarch64:
> +        if (!enforce_exact_match)
> +        {
> +            if (core2 == ArchSpec::eCore_arm_arm64)
> +                return true;
> +            if (core2 == ArchSpec::eCore_arm_armv8)
> +                return true;
> +            try_inverse = false;
> +        }
> +        break;
> +
> +    case ArchSpec::eCore_arm_arm64:
> +        if (!enforce_exact_match)
> +        {
> +            if (core2 == ArchSpec::eCore_arm_aarch64)
> +                return true;
> +            if (core2 == ArchSpec::eCore_arm_armv8)
> +                return true;
> +            try_inverse = false;
> +        }
> +        break;
> +
>     default:
>         break;
>     }
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