[Lldb-commits] [lldb] r146746 - in /lldb/trunk: include/lldb/Core/ArchSpec.h source/Core/ArchSpec.cpp source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp

Greg Clayton gclayton at apple.com
Fri Dec 16 10:15:52 PST 2011


Author: gclayton
Date: Fri Dec 16 12:15:52 2011
New Revision: 146746

URL: http://llvm.org/viewvc/llvm-project?rev=146746&view=rev
Log:
Handle all of the "thumb" target triple architecture variants that llvm
handles.


Modified:
    lldb/trunk/include/lldb/Core/ArchSpec.h
    lldb/trunk/source/Core/ArchSpec.cpp
    lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp

Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=146746&r1=146745&r2=146746&view=diff
==============================================================================
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Fri Dec 16 12:15:52 2011
@@ -38,6 +38,7 @@
         eCore_arm_armv4,
         eCore_arm_armv4t,
         eCore_arm_armv5,
+        eCore_arm_armv5e,
         eCore_arm_armv5t,
         eCore_arm_armv6,
         eCore_arm_armv7,
@@ -45,7 +46,15 @@
         eCore_arm_armv7k,
         eCore_arm_armv7s,
         eCore_arm_xscale,  
-        eCore_thumb_generic,
+        eCore_thumb,
+        eCore_thumbv4t,
+        eCore_thumbv5,
+        eCore_thumbv5e,
+        eCore_thumbv6,
+        eCore_thumbv7,
+        eCore_thumbv7f,
+        eCore_thumbv7k,
+        eCore_thumbv7s,
         
         eCore_ppc_generic,
         eCore_ppc_ppc601,

Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=146746&r1=146745&r2=146746&view=diff
==============================================================================
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Fri Dec 16 12:15:52 2011
@@ -47,6 +47,7 @@
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv4       , "armv4"     },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv4t      , "armv4t"    },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv5       , "armv5"     },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv5e      , "armv5e"    },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv5t      , "armv5t"    },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv6       , "armv6"     },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv7       , "armv7"     },
@@ -54,7 +55,16 @@
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv7k      , "armv7k"    },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_armv7s      , "armv7s"    },
     { eByteOrderLittle, 4, 2, 4, llvm::Triple::arm    , ArchSpec::eCore_arm_xscale      , "xscale"    },
-    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumb_generic   , "thumb"     },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumb           , "thumb"     },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv4t        , "thumbv4t"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv5         , "thumbv5"   },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv5e        , "thumbv5e"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv6         , "thumbv6"   },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7         , "thumbv7"   },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7f        , "thumbv7f"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7k        , "thumbv7k"  },
+    { eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb  , ArchSpec::eCore_thumbv7s        , "thumbv7s"  },
+    
     
     { eByteOrderLittle, 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_generic     , "ppc"       },
     { eByteOrderLittle, 4, 4, 4, llvm::Triple::ppc    , ArchSpec::eCore_ppc_ppc601      , "ppc601"    },
@@ -135,14 +145,25 @@
     { ArchSpec::eCore_arm_generic     , llvm::MachO::CPUTypeARM       , CPU_ANY },
     { ArchSpec::eCore_arm_generic     , llvm::MachO::CPUTypeARM       , 0       },
     { ArchSpec::eCore_arm_armv4       , llvm::MachO::CPUTypeARM       , 5       },
+    { ArchSpec::eCore_arm_armv4t      , llvm::MachO::CPUTypeARM       , 5       },
     { ArchSpec::eCore_arm_armv6       , llvm::MachO::CPUTypeARM       , 6       },
     { ArchSpec::eCore_arm_armv5       , llvm::MachO::CPUTypeARM       , 7       },
+    { ArchSpec::eCore_arm_armv5e      , llvm::MachO::CPUTypeARM       , 7       },
+    { ArchSpec::eCore_arm_armv5t      , llvm::MachO::CPUTypeARM       , 7       },
     { ArchSpec::eCore_arm_xscale      , llvm::MachO::CPUTypeARM       , 8       },
     { ArchSpec::eCore_arm_armv7       , llvm::MachO::CPUTypeARM       , 9       },
     { ArchSpec::eCore_arm_armv7f      , llvm::MachO::CPUTypeARM       , 10      },
     { ArchSpec::eCore_arm_armv7k      , llvm::MachO::CPUTypeARM       , 12      },
     { ArchSpec::eCore_arm_armv7s      , llvm::MachO::CPUTypeARM       , 11      },
-    { ArchSpec::eCore_thumb_generic   , llvm::MachO::CPUTypeARM       , 0       },
+    { ArchSpec::eCore_thumb           , llvm::MachO::CPUTypeARM       , 0       },
+    { ArchSpec::eCore_thumbv4t        , llvm::MachO::CPUTypeARM       , 5       },
+    { ArchSpec::eCore_thumbv5         , llvm::MachO::CPUTypeARM       , 7       },
+    { ArchSpec::eCore_thumbv5e        , llvm::MachO::CPUTypeARM       , 7       },
+    { ArchSpec::eCore_thumbv6         , llvm::MachO::CPUTypeARM       , 6       },
+    { ArchSpec::eCore_thumbv7         , llvm::MachO::CPUTypeARM       , 9       },
+    { ArchSpec::eCore_thumbv7f        , llvm::MachO::CPUTypeARM       , 10      },
+    { ArchSpec::eCore_thumbv7k        , llvm::MachO::CPUTypeARM       , 12      },
+    { ArchSpec::eCore_thumbv7s        , llvm::MachO::CPUTypeARM       , 11      },
     { ArchSpec::eCore_ppc_generic     , llvm::MachO::CPUTypePowerPC   , CPU_ANY },
     { ArchSpec::eCore_ppc_generic     , llvm::MachO::CPUTypePowerPC   , 0       },
     { ArchSpec::eCore_ppc_ppc601      , llvm::MachO::CPUTypePowerPC   , 1       },

Modified: lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp
URL: http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp?rev=146746&r1=146745&r2=146746&view=diff
==============================================================================
--- lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp (original)
+++ lldb/trunk/source/Plugins/Disassembler/llvm/DisassemblerLLVM.cpp Fri Dec 16 12:15:52 2011
@@ -693,7 +693,7 @@
 		// addresses.
         if (llvm_arch == llvm::Triple::arm)
         {
-            if (EDGetDisassembler(&m_disassembler_thumb, "thumb-apple-darwin", kEDAssemblySyntaxARMUAL))
+            if (EDGetDisassembler(&m_disassembler_thumb, "thumbv7-apple-darwin", kEDAssemblySyntaxARMUAL))
                 m_disassembler_thumb = NULL;
         }
     }





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