<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Jul 14, 2016, at 20:03, Aaron Watry <<a href="mailto:awatry@gmail.com" class="">awatry@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Re-adding libclc to CC list.... oops.<br class=""><div class=""><div class="gmail_extra"><br class=""><div class="gmail_quote">On Thu, Jul 14, 2016 at 10:03 PM, Aaron Watry <span dir="ltr" class=""><<a href="mailto:awatry@gmail.com" target="_blank" class="">awatry@gmail.com</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class=""><div class=""><div class=""><div class=""><div style="margin-left:40px" class="">From 02c998f017107153c6dc78b8eb58192bfc338d80 Mon Sep 17 00:00:00 2001<br class="">From: Matt Arsenault <<a href="mailto:matthew.arsenault@amd.com" class="">matthew.arsenault@Amd.com</a>><br class="">Date: Wed, 13 Jul 2016 21:07:53 -0700<br class="">Subject: [PATCH] R600: Use new barrier intrinsic<br class=""><br class="">---<br class=""> r600/lib/synchronization/barrier_impl.ll | 7 +++----<br class=""> 1 file changed, 3 insertions(+), 4 deletions(-)<br class=""><br class="">diff --git a/r600/lib/synchronization/barrier_impl.ll b/r600/lib/synchronization/barrier_impl.ll<br class="">index 825b2eb..9b8fefb 100644<br class="">--- a/r600/lib/synchronization/barrier_impl.ll<br class="">+++ b/r600/lib/synchronization/barrier_impl.ll<br class="">@@ -1,7 +1,6 @@<br class=""> declare i32 @__clc_clk_local_mem_fence() #1<br class=""> declare i32 @__clc_clk_global_mem_fence() #1<br class="">-declare void @llvm.AMDGPU.barrier.local() #0<br class="">-declare void @llvm.AMDGPU.barrier.global() #0<br class="">+declare void @llvm.r600.group.barrier() #0<br class=""> <br class=""> define void @barrier(i32 %flags) #2 {<br class=""> barrier_local_test:<br class="">@@ -11,7 +10,7 @@ barrier_local_test:<br class=""> br i1 %1, label %barrier_local, label %barrier_global_test<br class=""> <br class=""> barrier_local:<br class="">- call void @llvm.AMDGPU.barrier.local()<br class="">+ call void @llvm.r600.group.barrier()<br class=""><br class=""></div>Please pardon my ignorance, but does the new intrinsic handle synchronizing writes/reads to local/global memory along with thread synchronization?<br class=""><br class=""></div>If that is the case, could we modify the barrier_local portion to jump straight to done, so that we don't end up inserting two barriers if someone calls<br class=""></div>barrier(CLK_GLOBAL_MEM_FENCE | CLK_LOCAL_MEM_FENCE);<br class=""><br class=""></div><div class="">I don't have my NI card installed at the moment, but could if necessary to test things out.<br class=""></div><div class=""><br class=""></div>--Aaron<br class=""><div class=""><div class=""><div class=""><div class=""><div class=""><div class=""><div style="margin-left:40px" class=""><br class=""></div></div></div></div></div></div></div></div></blockquote></div></div></div></div></div></blockquote><br class=""></div><div>No, but the old intrinsics didn’t either. There is only one synchronization instruction, the memory fence is a different problem. I don’t think it actually matters with the constraint that global memory is only consistent within a workgroup, although I”m less sure how the old hardware caches worked</div><div><br class=""></div><div>-Matt</div><br class=""></body></html>