[flang-commits] [compiler-rt] [llvm] [libcxx] [clang] [mlir] [openmp] [libcxxabi] [flang] [clang-tools-extra] [libc] [AArch64] Add custom lowering for load <3 x i8>. (PR #78632)

Yingchi Long via flang-commits flang-commits at lists.llvm.org
Thu Jan 25 23:47:09 PST 2024


================
@@ -21248,6 +21297,51 @@ static SDValue foldTruncStoreOfExt(SelectionDAG &DAG, SDNode *N) {
   return SDValue();
 }
 
+// A custom combine to lower load <3 x i8> as the more efficient sequence
+// below:
+//    ldrb wX, [x0, #2]
+//    ldrh wY, [x0]
+//    orr wX, wY, wX, lsl #16
+//    fmov s0, wX
+//
+static SDValue combineV3I8LoadExt(LoadSDNode *LD, SelectionDAG &DAG) {
+  EVT MemVT = LD->getMemoryVT();
+  if (MemVT != EVT::getVectorVT(*DAG.getContext(), MVT::i8, 3) ||
+      LD->getOriginalAlign() >= 4)
+    return SDValue();
+
+  SDLoc DL(LD);
+  MachineFunction &MF = DAG.getMachineFunction();
+  SDValue Chain = LD->getChain();
+  SDValue BasePtr = LD->getBasePtr();
+  MachineMemOperand *MMO = LD->getMemOperand();
+  assert(LD->getOffset().isUndef() && "undef offset expected");
----------------
inclyc wrote:

I recently encountered a miscompilation when the program is relatively large, related to this assertion (not in aarch64 backend).

Should we use some if-branch to detect this, and return `SDValue()`?

I'm not sure how to construct indexed load directly in IR, perhaps I may make a reproducer from the test suite.

https://github.com/llvm/llvm-project/pull/78632


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