[flang-commits] [mlir] [flang] [mlir][openacc] Simplify IR with acc.loop control (PR #80387)
Valentin Clement バレンタイン クレメン via flang-commits
flang-commits at lists.llvm.org
Mon Feb 5 14:06:14 PST 2024
https://github.com/clementval updated https://github.com/llvm/llvm-project/pull/80387
>From 550538b355f74e2222e9ff0e81333f54692a1d5a Mon Sep 17 00:00:00 2001
From: Valentin Clement <clementval at gmail.com>
Date: Thu, 1 Feb 2024 15:15:59 -0800
Subject: [PATCH 1/2] [mlir][openacc] Simplify IR with acc.loop control
---
flang/test/Lower/OpenACC/acc-kernels-loop.f90 | 6 +-
flang/test/Lower/OpenACC/acc-loop.f90 | 56 ++++++++--------
.../test/Lower/OpenACC/acc-parallel-loop.f90 | 6 +-
flang/test/Lower/OpenACC/acc-serial-loop.f90 | 6 +-
flang/test/Lower/OpenACC/acc-update.f90 | 4 +-
.../mlir/Dialect/OpenACC/OpenACCOps.td | 1 +
mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp | 55 ++++++++--------
mlir/test/Dialect/OpenACC/canonicalize.mlir | 4 +-
mlir/test/Dialect/OpenACC/invalid.mlir | 24 +++----
mlir/test/Dialect/OpenACC/ops.mlir | 64 +++++++++----------
10 files changed, 114 insertions(+), 112 deletions(-)
diff --git a/flang/test/Lower/OpenACC/acc-kernels-loop.f90 b/flang/test/Lower/OpenACC/acc-kernels-loop.f90
index 24f537ccec224c..e85065e54bc362 100644
--- a/flang/test/Lower/OpenACC/acc-kernels-loop.f90
+++ b/flang/test/Lower/OpenACC/acc-kernels-loop.f90
@@ -466,7 +466,7 @@ subroutine acc_kernels_loop
END DO
! CHECK: acc.kernels {
-! CHECK: acc.loop gang() {{.*}} {
+! CHECK: acc.loop gang {{.*}} {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.terminator
@@ -515,7 +515,7 @@ subroutine acc_kernels_loop
a(i) = b(i)
END DO
! CHECK: acc.kernels {
-! CHECK: acc.loop vector() {{.*}} {
+! CHECK: acc.loop vector {{.*}} {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.terminator
@@ -553,7 +553,7 @@ subroutine acc_kernels_loop
END DO
! CHECK: acc.kernels {
-! CHECK: acc.loop worker() {{.*}} {
+! CHECK: acc.loop worker {{.*}} {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.terminator
diff --git a/flang/test/Lower/OpenACC/acc-loop.f90 b/flang/test/Lower/OpenACC/acc-loop.f90
index 28da9f99282ced..1c64fab3536bb9 100644
--- a/flang/test/Lower/OpenACC/acc-loop.f90
+++ b/flang/test/Lower/OpenACC/acc-loop.f90
@@ -27,7 +27,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
@@ -36,7 +36,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>, seq = [#acc.device_type<none>]}
@@ -45,7 +45,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {auto_ = [#acc.device_type<none>], inclusiveUpperbound = array<i1: true>}
@@ -54,7 +54,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>, independent = [#acc.device_type<none>]}
@@ -63,7 +63,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop gang() private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop gang private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -73,7 +73,7 @@ program acc_loop
END DO
! CHECK: [[GANGNUM1:%.*]] = arith.constant 8 : i32
-! CHECK-NEXT: acc.loop gang({num=[[GANGNUM1]] : i32}) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK-NEXT: acc.loop gang({num=[[GANGNUM1]] : i32}) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -83,7 +83,7 @@ program acc_loop
END DO
! CHECK: [[GANGNUM2:%.*]] = fir.load %{{.*}} : !fir.ref<i32>
-! CHECK-NEXT: acc.loop gang({num=[[GANGNUM2]] : i32}) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK-NEXT: acc.loop gang({num=[[GANGNUM2]] : i32}) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -92,7 +92,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop gang({num=%{{.*}} : i32, static=%{{.*}} : i32}) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop gang({num=%{{.*}} : i32, static=%{{.*}} : i32}) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -101,7 +101,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop vector() private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop vector private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -111,7 +111,7 @@ program acc_loop
END DO
! CHECK: [[CONSTANT128:%.*]] = arith.constant 128 : i32
-! CHECK: acc.loop vector([[CONSTANT128]] : i32) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop vector([[CONSTANT128]] : i32) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: }{{$}}
@@ -121,7 +121,7 @@ program acc_loop
END DO
! CHECK: [[VECTORLENGTH:%.*]] = fir.load %{{.*}} : !fir.ref<i32>
-! CHECK: acc.loop vector([[VECTORLENGTH]] : i32) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop vector([[VECTORLENGTH]] : i32) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -130,7 +130,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop worker() private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop worker private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -140,7 +140,7 @@ program acc_loop
END DO
! CHECK: [[WORKER128:%.*]] = arith.constant 128 : i32
-! CHECK: acc.loop worker([[WORKER128]] : i32) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop worker([[WORKER128]] : i32) private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -149,7 +149,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -158,7 +158,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -167,7 +167,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>, @privatization_ref_10x10xf32 -> %{{.*}} : !fir.ref<!fir.array<10x10xf32>>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -177,7 +177,7 @@ program acc_loop
END DO
! CHECK: [[TILESIZE:%.*]] = arith.constant 2 : i32
-! CHECK: acc.loop {{.*}} tile({[[TILESIZE]] : i32}) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} tile({[[TILESIZE]] : i32}) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -186,7 +186,7 @@ program acc_loop
a(i) = b(i)
END DO
! CHECK: [[TILESIZEM1:%.*]] = arith.constant -1 : i32
-! CHECK: acc.loop {{.*}} tile({[[TILESIZEM1]] : i32}) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} tile({[[TILESIZEM1]] : i32}) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -199,7 +199,7 @@ program acc_loop
! CHECK: [[TILESIZE1:%.*]] = arith.constant 2 : i32
! CHECK: [[TILESIZE2:%.*]] = arith.constant 2 : i32
-! CHECK: acc.loop {{.*}} tile({[[TILESIZE1]] : i32, [[TILESIZE2]] : i32}) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} tile({[[TILESIZE1]] : i32, [[TILESIZE2]] : i32}) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -208,7 +208,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop {{.*}} tile({%{{.*}} : i32}) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} tile({%{{.*}} : i32}) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -219,7 +219,7 @@ program acc_loop
END DO
END DO
-! CHECK: acc.loop {{.*}} tile({%{{.*}} : i32, %{{.*}} : i32}) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} tile({%{{.*}} : i32, %{{.*}} : i32}) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -230,7 +230,7 @@ program acc_loop
END DO
END DO
-! CHECK: acc.loop {{.*}} (%arg0 : i32, %arg1 : i32) = (%{{.*}} : i32, i32) to (%{{.*}} : i32, i32) step (%{{.*}} : i32, i32) {
+! CHECK: acc.loop {{.*}} control(%arg0 : i32, %arg1 : i32) = (%{{.*}} : i32, i32) to (%{{.*}} : i32, i32) step (%{{.*}} : i32, i32) {
! CHECK: fir.store %arg0 to %{{.*}} : !fir.ref<i32>
! CHECK: fir.store %arg1 to %{{.*}} : !fir.ref<i32>
! CHECK: acc.yield
@@ -244,8 +244,8 @@ program acc_loop
END DO
END DO
-! CHECK: acc.loop {{.*}} (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
-! CHECK: acc.loop {{.*}} (%arg1 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop {{.*}} control(%arg1 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
! CHECK: acc.yield
@@ -257,7 +257,7 @@ program acc_loop
reduction_i = 1
end do
-! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) reduction(@reduction_add_ref_f32 -> %{{.*}} : !fir.ref<f32>, @reduction_mul_ref_i32 -> %{{.*}} : !fir.ref<i32>) (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop private(@privatization_ref_i32 -> %{{.*}} : !fir.ref<i32>) reduction(@reduction_add_ref_f32 -> %{{.*}} : !fir.ref<f32>, @reduction_mul_ref_i32 -> %{{.*}} : !fir.ref<i32>) control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -266,7 +266,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop gang({dim=%{{.*}}, static=%{{.*}} : i32}) {{.*}} (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop gang({dim=%{{.*}}, static=%{{.*}} : i32}) {{.*}} control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -275,7 +275,7 @@ program acc_loop
a(i) = b(i)
END DO
-! CHECK: acc.loop gang({dim={{.*}} : i32}) {{.*}} (%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
+! CHECK: acc.loop gang({dim={{.*}} : i32}) {{.*}} control(%arg0 : i32) = (%{{.*}} : i32) to (%{{.*}} : i32) step (%{{.*}} : i32) {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
@@ -324,5 +324,5 @@ subroutine sub1(i, j, k)
! CHECK: %[[P_I:.*]] = acc.private varPtr(%[[DC_I]] : !fir.ref<i32>) -> !fir.ref<i32> {implicit = true, name = ""}
! CHECK: %[[P_J:.*]] = acc.private varPtr(%[[DC_J]] : !fir.ref<i32>) -> !fir.ref<i32> {implicit = true, name = ""}
! CHECK: %[[P_K:.*]] = acc.private varPtr(%[[DC_K]] : !fir.ref<i32>) -> !fir.ref<i32> {implicit = true, name = ""}
-! CHECK: acc.loop private(@privatization_ref_i32 -> %[[P_I]] : !fir.ref<i32>, @privatization_ref_i32 -> %[[P_J]] : !fir.ref<i32>, @privatization_ref_i32 -> %[[P_K]] : !fir.ref<i32>) (%{{.*}} : i32, %{{.*}} : i32, %{{.*}} : i32) = (%c1{{.*}}, %c1{{.*}}, %c1{{.*}} : i32, i32, i32) to (%c10{{.*}}, %c100{{.*}}, %c200{{.*}} : i32, i32, i32) step (%c1{{.*}}, %c1{{.*}}, %c1{{.*}} : i32, i32, i32)
+! CHECK: acc.loop private(@privatization_ref_i32 -> %[[P_I]] : !fir.ref<i32>, @privatization_ref_i32 -> %[[P_J]] : !fir.ref<i32>, @privatization_ref_i32 -> %[[P_K]] : !fir.ref<i32>) control(%{{.*}} : i32, %{{.*}} : i32, %{{.*}} : i32) = (%c1{{.*}}, %c1{{.*}}, %c1{{.*}} : i32, i32, i32) to (%c10{{.*}}, %c100{{.*}}, %c200{{.*}} : i32, i32, i32) step (%c1{{.*}}, %c1{{.*}}, %c1{{.*}} : i32, i32, i32)
! CHECK: } attributes {inclusiveUpperbound = array<i1: true, true, true>}
diff --git a/flang/test/Lower/OpenACC/acc-parallel-loop.f90 b/flang/test/Lower/OpenACC/acc-parallel-loop.f90
index 5968b24782fb4b..39f18307486aa3 100644
--- a/flang/test/Lower/OpenACC/acc-parallel-loop.f90
+++ b/flang/test/Lower/OpenACC/acc-parallel-loop.f90
@@ -481,7 +481,7 @@ subroutine acc_parallel_loop
END DO
! CHECK: acc.parallel {
-! CHECK: acc.loop gang()
+! CHECK: acc.loop gang
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.yield
@@ -530,7 +530,7 @@ subroutine acc_parallel_loop
a(i) = b(i)
END DO
! CHECK: acc.parallel {
-! CHECK: acc.loop vector()
+! CHECK: acc.loop vector
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.yield
@@ -569,7 +569,7 @@ subroutine acc_parallel_loop
END DO
! CHECK: acc.parallel {
-! CHECK: acc.loop worker() {{.*}} {
+! CHECK: acc.loop worker {{.*}} {
! CHECK-NOT: fir.do_loop
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
diff --git a/flang/test/Lower/OpenACC/acc-serial-loop.f90 b/flang/test/Lower/OpenACC/acc-serial-loop.f90
index 2869077bcb1ff8..77f5e1eaa7c821 100644
--- a/flang/test/Lower/OpenACC/acc-serial-loop.f90
+++ b/flang/test/Lower/OpenACC/acc-serial-loop.f90
@@ -422,7 +422,7 @@ subroutine acc_serial_loop
END DO
! CHECK: acc.serial {
-! CHECK: acc.loop gang() {{.*}} {
+! CHECK: acc.loop gang {{.*}} {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.yield
@@ -471,7 +471,7 @@ subroutine acc_serial_loop
a(i) = b(i)
END DO
! CHECK: acc.serial {
-! CHECK: acc.loop vector() {{.*}} {
+! CHECK: acc.loop vector {{.*}} {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.yield
@@ -509,7 +509,7 @@ subroutine acc_serial_loop
END DO
! CHECK: acc.serial {
-! CHECK: acc.loop worker() {{.*}} {
+! CHECK: acc.loop worker {{.*}} {
! CHECK: acc.yield
! CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}{{$}}
! CHECK: acc.yield
diff --git a/flang/test/Lower/OpenACC/acc-update.f90 b/flang/test/Lower/OpenACC/acc-update.f90
index 0c30ea5d44c614..bab21f82152b2b 100644
--- a/flang/test/Lower/OpenACC/acc-update.f90
+++ b/flang/test/Lower/OpenACC/acc-update.f90
@@ -61,7 +61,7 @@ subroutine acc_update
!$acc update host(a) async
! CHECK: %[[DEVPTR_A:.*]] = acc.getdeviceptr varPtr(%[[DECLA]]#0 : !fir.ref<!fir.array<10x10xf32>>) bounds(%{{.*}}, %{{.*}}) -> !fir.ref<!fir.array<10x10xf32>> {dataClause = #acc<data_clause acc_update_host>, name = "a", structured = false}
-! CHECK: acc.update async() dataOperands(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>)
+! CHECK: acc.update async dataOperands(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>)
! CHECK: acc.update_host accPtr(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>) bounds(%{{.*}}, %{{.*}}) to varPtr(%[[DECLA]]#0 : !fir.ref<!fir.array<10x10xf32>>) {name = "a", structured = false}
!$acc update host(a) wait
@@ -71,7 +71,7 @@ subroutine acc_update
!$acc update host(a) async wait
! CHECK: %[[DEVPTR_A:.*]] = acc.getdeviceptr varPtr(%[[DECLA]]#0 : !fir.ref<!fir.array<10x10xf32>>) bounds(%{{.*}}, %{{.*}}) -> !fir.ref<!fir.array<10x10xf32>> {dataClause = #acc<data_clause acc_update_host>, name = "a", structured = false}
-! CHECK: acc.update async() wait dataOperands(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>)
+! CHECK: acc.update async wait dataOperands(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>)
! CHECK: acc.update_host accPtr(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>) bounds(%{{.*}}, %{{.*}}) to varPtr(%[[DECLA]]#0 : !fir.ref<!fir.array<10x10xf32>>) {name = "a", structured = false}
!$acc update host(a) async(1)
diff --git a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
index af72fb6e2ac228..6da7a742bbed8c 100644
--- a/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
+++ b/mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
@@ -1585,6 +1585,7 @@ def OpenACC_LoopOp : OpenACC_Op<"loop",
static StringRef getGangNumKeyword() { return "num"; }
static StringRef getGangDimKeyword() { return "dim"; }
static StringRef getGangStaticKeyword() { return "static"; }
+ static StringRef getControlKeyword() { return "control"; }
/// The number of private and reduction operands.
unsigned getNumDataOperands();
diff --git a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
index ae5da686f8595a..18187e7d4f66cd 100644
--- a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+++ b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
@@ -1211,8 +1211,14 @@ static ParseResult parseDeviceTypeOperandsWithKeywordOnly(
llvm::SmallVector<mlir::Attribute> keywordOnlyDeviceTypeAttributes;
bool needCommaBeforeOperands = false;
- if (failed(parser.parseOptionalLParen()))
- return failure();
+ if (failed(parser.parseOptionalLParen())) {
+ // Keyword only
+ keywordOnlyDeviceTypeAttributes.push_back(mlir::acc::DeviceTypeAttr::get(
+ parser.getContext(), mlir::acc::DeviceType::None));
+ keywordOnlyDeviceType =
+ ArrayAttr::get(parser.getContext(), keywordOnlyDeviceTypeAttributes);
+ return success();
+ }
// Parse keyword only attributes
if (succeeded(parser.parseOptionalLSquare())) {
@@ -1227,13 +1233,6 @@ static ParseResult parseDeviceTypeOperandsWithKeywordOnly(
if (parser.parseRSquare())
return failure();
needCommaBeforeOperands = true;
- } else if (succeeded(parser.parseOptionalRParen())) {
- // Keyword only
- keywordOnlyDeviceTypeAttributes.push_back(mlir::acc::DeviceTypeAttr::get(
- parser.getContext(), mlir::acc::DeviceType::None));
- keywordOnlyDeviceType =
- ArrayAttr::get(parser.getContext(), keywordOnlyDeviceTypeAttributes);
- return success();
}
if (needCommaBeforeOperands && failed(parser.parseComma()))
@@ -1270,13 +1269,12 @@ static void printDeviceTypeOperandsWithKeywordOnly(
mlir::TypeRange types, std::optional<mlir::ArrayAttr> deviceTypes,
std::optional<mlir::ArrayAttr> keywordOnlyDeviceTypes) {
- p << "(";
if (operands.begin() == operands.end() &&
hasOnlyDeviceTypeNone(keywordOnlyDeviceTypes)) {
- p << ")";
return;
}
+ p << "(";
printDeviceTypes(p, keywordOnlyDeviceTypes);
if (hasDeviceTypeValues(keywordOnlyDeviceTypes) &&
hasDeviceTypeValues(deviceTypes))
@@ -1556,8 +1554,14 @@ static ParseResult parseGangClause(
bool needCommaBetweenValues = false;
bool needCommaBeforeOperands = false;
- if (failed(parser.parseOptionalLParen()))
- return failure();
+ if (failed(parser.parseOptionalLParen())) {
+ // Gang only keyword
+ gangOnlyDeviceTypeAttributes.push_back(mlir::acc::DeviceTypeAttr::get(
+ parser.getContext(), mlir::acc::DeviceType::None));
+ gangOnlyDeviceType =
+ ArrayAttr::get(parser.getContext(), gangOnlyDeviceTypeAttributes);
+ return success();
+ }
// Parse gang only attributes
if (succeeded(parser.parseOptionalLSquare())) {
@@ -1572,13 +1576,6 @@ static ParseResult parseGangClause(
if (parser.parseRSquare())
return failure();
needCommaBeforeOperands = true;
- } else if (succeeded(parser.parseOptionalRParen())) {
- // Gang only keyword
- gangOnlyDeviceTypeAttributes.push_back(mlir::acc::DeviceTypeAttr::get(
- parser.getContext(), mlir::acc::DeviceType::None));
- gangOnlyDeviceType =
- ArrayAttr::get(parser.getContext(), gangOnlyDeviceTypeAttributes);
- return success();
}
auto argNum = mlir::acc::GangArgTypeAttr::get(parser.getContext(),
@@ -1678,13 +1675,13 @@ void printGangClause(OpAsmPrinter &p, Operation *op,
std::optional<mlir::DenseI32ArrayAttr> segments,
std::optional<mlir::ArrayAttr> gangOnlyDeviceTypes) {
- p << "(";
if (operands.begin() == operands.end() &&
hasOnlyDeviceTypeNone(gangOnlyDeviceTypes)) {
- p << ")";
return;
}
+ p << "(";
+
printDeviceTypes(p, gangOnlyDeviceTypes);
if (hasDeviceTypeValues(gangOnlyDeviceTypes) &&
@@ -1991,8 +1988,10 @@ llvm::SmallVector<mlir::Region *> acc::LoopOp::getLoopRegions() {
return {&getRegion()};
}
-/// loop-control ::= `(` ssa-id-and-type-list `)` `=` `(` ssa-id-and-type-list
-/// `)` `to` `(` ssa-id-and-type-list `)` `step` `(` ssa-id-and-type-list `)`
+/// loop-control ::= `control` `(` ssa-id-and-type-list `)` `=`
+/// `(` ssa-id-and-type-list `)` `to` `(` ssa-id-and-type-list `)` `step`
+/// `(` ssa-id-and-type-list `)`
+/// region
ParseResult
parseLoopControl(OpAsmParser &parser, Region ®ion,
SmallVectorImpl<OpAsmParser::UnresolvedOperand> &lowerbound,
@@ -2003,8 +2002,10 @@ parseLoopControl(OpAsmParser &parser, Region ®ion,
SmallVectorImpl<Type> &stepType) {
SmallVector<OpAsmParser::Argument> inductionVars;
- if (succeeded(parser.parseOptionalLParen())) {
- if (parser.parseArgumentList(inductionVars, OpAsmParser::Delimiter::None,
+ if (succeeded(
+ parser.parseOptionalKeyword(acc::LoopOp::getControlKeyword()))) {
+ if (parser.parseLParen() ||
+ parser.parseArgumentList(inductionVars, OpAsmParser::Delimiter::None,
/*allowType=*/true) ||
parser.parseRParen() || parser.parseEqual() || parser.parseLParen() ||
parser.parseOperandList(lowerbound, inductionVars.size(),
@@ -2029,7 +2030,7 @@ void printLoopControl(OpAsmPrinter &p, Operation *op, Region ®ion,
ValueRange steps, TypeRange stepType) {
ValueRange regionArgs = region.front().getArguments();
if (!regionArgs.empty()) {
- p << "(";
+ p << acc::LoopOp::getControlKeyword() << "(";
llvm::interleaveComma(regionArgs, p,
[&p](Value v) { p << v << " : " << v.getType(); });
p << ") = (" << lowerbound << " : " << lowerboundType << ") to ("
diff --git a/mlir/test/Dialect/OpenACC/canonicalize.mlir b/mlir/test/Dialect/OpenACC/canonicalize.mlir
index 4522ffb252a62e..e43a27f6b9e89a 100644
--- a/mlir/test/Dialect/OpenACC/canonicalize.mlir
+++ b/mlir/test/Dialect/OpenACC/canonicalize.mlir
@@ -114,10 +114,10 @@ func.func @testhostdataop(%a: memref<f32>, %ifCond: i1) -> () {
%2 = arith.constant 10 : i32
%false = arith.constant false
acc.host_data dataOperands(%0 : memref<f32>) if(%false) {
- acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.yield
} attributes { inclusiveUpperbound = array<i1: true> }
- acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+ acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.yield
} attributes { inclusiveUpperbound = array<i1: true> }
acc.terminator
diff --git a/mlir/test/Dialect/OpenACC/invalid.mlir b/mlir/test/Dialect/OpenACC/invalid.mlir
index 16df33eec642ce..70747b7e2acf4b 100644
--- a/mlir/test/Dialect/OpenACC/invalid.mlir
+++ b/mlir/test/Dialect/OpenACC/invalid.mlir
@@ -3,7 +3,7 @@
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq = [#acc.device_type<none>], gang = [#acc.device_type<none>]}
@@ -13,7 +13,7 @@ acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq = [#acc.device_type<none>], worker = [#acc.device_type<none>]}
@@ -23,7 +23,7 @@ acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq = [#acc.device_type<none>], vector = [#acc.device_type<none>]}
@@ -33,7 +33,7 @@ acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq = [#acc.device_type<none>], worker = [#acc.device_type<none>], gang = [#acc.device_type<none>]}
@@ -43,7 +43,7 @@ acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq = [#acc.device_type<none>], vector = [#acc.device_type<none>], gang = [#acc.device_type<none>]}
@@ -53,7 +53,7 @@ acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{gang, worker or vector cannot appear with the seq attr}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {seq = [#acc.device_type<none>], vector = [#acc.device_type<none>], worker = [#acc.device_type<none>]}
@@ -100,7 +100,7 @@ acc.loop {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{only one of "auto", "independent", "seq" can be present at the same time}}
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
acc.yield
} attributes {auto_ = [#acc.device_type<none>], seq = [#acc.device_type<none>], inclusiveUpperbound = array<i1: true>}
@@ -164,7 +164,7 @@ acc.parallel {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32){
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32){
// expected-error at +1 {{'acc.init' op cannot be nested in a compute operation}}
acc.init
acc.yield
@@ -182,7 +182,7 @@ acc.parallel {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
// expected-error at +1 {{'acc.shutdown' op cannot be nested in a compute operation}}
acc.shutdown
acc.yield
@@ -192,7 +192,7 @@ acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
-acc.loop (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() ({
// expected-error at +1 {{'acc.shutdown' op cannot be nested in a compute operation}}
acc.shutdown
@@ -405,7 +405,7 @@ acc.firstprivate.recipe @privatization_i32 : i32 init {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{expected ')'}}
-acc.loop gang({static=%i64Value: i64, num=%i64Value: i64} (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop gang({static=%i64Value: i64, num=%i64Value: i64} control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
}
@@ -476,7 +476,7 @@ acc.reduction.recipe @reduction_i64 : i64 reduction_operator<add> init {
%1 = arith.constant 1 : i32
%2 = arith.constant 10 : i32
// expected-error at +1 {{new value expected after comma}}
-acc.loop gang({static=%i64Value: i64, ) (%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
+acc.loop gang({static=%i64Value: i64, ) control(%iv : i32) = (%1 : i32) to (%2 : i32) step (%1 : i32) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
}
diff --git a/mlir/test/Dialect/OpenACC/ops.mlir b/mlir/test/Dialect/OpenACC/ops.mlir
index 4e6ed8645cdbce..1739b3de3e65fd 100644
--- a/mlir/test/Dialect/OpenACC/ops.mlir
+++ b/mlir/test/Dialect/OpenACC/ops.mlir
@@ -11,7 +11,7 @@ func.func @compute1(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x
%async = arith.constant 1 : i64
acc.parallel async(%async: i64) {
- acc.loop gang() vector() (%arg3 : index, %arg4 : index, %arg5 : index) = (%c0, %c0, %c0 : index, index, index) to (%c10, %c10, %c10 : index, index, index) step (%c1, %c1, %c1 : index, index, index) {
+ acc.loop gang vector control(%arg3 : index, %arg4 : index, %arg5 : index) = (%c0, %c0, %c0 : index, index, index) to (%c10, %c10, %c10 : index, index, index) step (%c1, %c1, %c1 : index, index, index) {
%a = memref.load %A[%arg3, %arg5] : memref<10x10xf32>
%b = memref.load %B[%arg5, %arg4] : memref<10x10xf32>
%cij = memref.load %C[%arg3, %arg4] : memref<10x10xf32>
@@ -32,7 +32,7 @@ func.func @compute1(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x
// CHECK-NEXT: %{{.*}} = arith.constant 1 : index
// CHECK-NEXT: [[ASYNC:%.*]] = arith.constant 1 : i64
// CHECK-NEXT: acc.parallel async([[ASYNC]] : i64) {
-// CHECK-NEXT: acc.loop gang() vector() (%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
+// CHECK-NEXT: acc.loop gang vector control(%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32>
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32>
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32>
@@ -54,7 +54,7 @@ func.func @compute2(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x
%c1 = arith.constant 1 : index
acc.parallel {
- acc.loop (%arg3 : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop control(%arg3 : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
scf.for %arg4 = %c0 to %c10 step %c1 {
scf.for %arg5 = %c0 to %c10 step %c1 {
%a = memref.load %A[%arg3, %arg5] : memref<10x10xf32>
@@ -78,7 +78,7 @@ func.func @compute2(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x
// CHECK-NEXT: %{{.*}} = arith.constant 10 : index
// CHECK-NEXT: %{{.*}} = arith.constant 1 : index
// CHECK-NEXT: acc.parallel {
-// CHECK-NEXT: acc.loop (%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}})
+// CHECK-NEXT: acc.loop control(%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}})
// CHECK-NEXT: scf.for %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} {
// CHECK-NEXT: scf.for %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} {
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32>
@@ -122,8 +122,8 @@ func.func @compute3(%a: memref<10x10xf32>, %b: memref<10x10xf32>, %c: memref<10x
acc.data dataOperands(%pa, %pb, %pc, %pd: memref<10x10xf32>, memref<10x10xf32>, memref<10xf32>, memref<10xf32>) {
%private = acc.private varPtr(%c : memref<10xf32>) -> memref<10xf32>
acc.parallel num_gangs({%numGangs: i64}) num_workers(%numWorkers: i64 [#acc.device_type<nvidia>]) private(@privatization_memref_10_f32 -> %private : memref<10xf32>) {
- acc.loop gang() (%x : index) = (%lb : index) to (%c10 : index) step (%st : index) {
- acc.loop worker() (%y : index) = (%lb : index) to (%c10 : index) step (%st : index) {
+ acc.loop gang control(%x : index) = (%lb : index) to (%c10 : index) step (%st : index) {
+ acc.loop worker control(%y : index) = (%lb : index) to (%c10 : index) step (%st : index) {
%axy = memref.load %a[%x, %y] : memref<10x10xf32>
%bxy = memref.load %b[%x, %y] : memref<10x10xf32>
%tmp = arith.addf %axy, %bxy : f32
@@ -131,7 +131,7 @@ func.func @compute3(%a: memref<10x10xf32>, %b: memref<10x10xf32>, %c: memref<10x
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop (%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
+ acc.loop control(%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
// for i = 0 to 10 step 1
// d[x] += c[i]
%ci = memref.load %c[%i] : memref<10xf32>
@@ -159,15 +159,15 @@ func.func @compute3(%a: memref<10x10xf32>, %b: memref<10x10xf32>, %c: memref<10x
// CHECK: acc.data dataOperands(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : memref<10x10xf32>, memref<10x10xf32>, memref<10xf32>, memref<10xf32>) {
// CHECK-NEXT: %[[P_ARG2:.*]] = acc.private varPtr([[ARG2]] : memref<10xf32>) -> memref<10xf32>
// CHECK-NEXT: acc.parallel num_gangs({[[NUMGANG]] : i64}) num_workers([[NUMWORKERS]] : i64 [#acc.device_type<nvidia>]) private(@privatization_memref_10_f32 -> %[[P_ARG2]] : memref<10xf32>) {
-// CHECK-NEXT: acc.loop gang() (%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
-// CHECK-NEXT: acc.loop worker() (%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
+// CHECK-NEXT: acc.loop gang control(%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
+// CHECK-NEXT: acc.loop worker control(%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32>
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32>
// CHECK-NEXT: %{{.*}} = arith.addf %{{.*}}, %{{.*}} : f32
// CHECK-NEXT: memref.store %{{.*}}, %{{.*}}[%{{.*}}] : memref<10xf32>
// CHECK-NEXT: acc.yield
// CHECK-NEXT: } attributes {inclusiveUpperbound = array<i1: true>}
-// CHECK-NEXT: acc.loop (%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
+// CHECK-NEXT: acc.loop control(%{{.*}}) = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) {
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}] : memref<10xf32>
// CHECK-NEXT: %{{.*}} = memref.load %{{.*}}[%{{.*}}] : memref<10xf32>
// CHECK-NEXT: %{{.*}} = arith.addf %{{.*}}, %{{.*}} : f32
@@ -193,72 +193,72 @@ func.func @testloopop(%a : memref<10xf32>) -> () {
%c10 = arith.constant 10 : index
%c1 = arith.constant 1 : index
- acc.loop gang() vector() worker() (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang vector worker control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({num=%i64Value: i64}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({num=%i64Value: i64}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({static=%i64Value: i64}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({static=%i64Value: i64}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop worker(%i64Value: i64) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop worker(%i64Value: i64) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop worker(%i32Value: i32) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop worker(%i32Value: i32) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop worker(%idxValue: index) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop worker(%idxValue: index) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop vector(%i64Value: i64) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop vector(%i64Value: i64) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop vector(%i32Value: i32) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop vector(%i32Value: i32) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop vector(%idxValue: index) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop vector(%idxValue: index) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({num=%i64Value: i64}) worker() vector() (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({num=%i64Value: i64}) worker vector control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({num=%i64Value: i64, static=%i64Value: i64}) worker(%i64Value: i64) vector(%i64Value: i64) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({num=%i64Value: i64, static=%i64Value: i64}) worker(%i64Value: i64) vector(%i64Value: i64) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({num=%i32Value: i32, static=%idxValue: index}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({num=%i32Value: i32, static=%idxValue: index}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop tile({%i64Value : i64, %i64Value : i64}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop tile({%i64Value : i64, %i64Value : i64}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop tile({%i32Value : i32, %i32Value : i32}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop tile({%i32Value : i32, %i32Value : i32}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({static=%i64Value: i64, num=%i64Value: i64}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({static=%i64Value: i64, num=%i64Value: i64}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
- acc.loop gang({dim=%i64Value : i64, static=%i64Value: i64}) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop gang({dim=%i64Value : i64, static=%i64Value: i64}) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
%b = acc.cache varPtr(%a : memref<10xf32>) -> memref<10xf32>
- acc.loop cache(%b : memref<10xf32>) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop cache(%b : memref<10xf32>) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
"test.openacc_dummy_op"() : () -> ()
acc.yield
} attributes {inclusiveUpperbound = array<i1: true>}
@@ -296,7 +296,7 @@ func.func @testloopop(%a : memref<10xf32>) -> () {
// CHECK: acc.loop vector([[IDXVALUE]] : index)
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
-// CHECK: acc.loop gang({num=[[I64VALUE]] : i64}) worker() vector()
+// CHECK: acc.loop gang({num=[[I64VALUE]] : i64}) worker vector
// CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield
// CHECK: acc.loop gang({num=[[I64VALUE]] : i64, static=[[I64VALUE]] : i64}) worker([[I64VALUE]] : i64) vector([[I64VALUE]] : i64)
@@ -329,7 +329,7 @@ func.func @acc_loop_multiple_block() {
%c10 = arith.constant 10 : index
%c1 = arith.constant 1 : index
acc.parallel {
- acc.loop (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
%c1_1 = arith.constant 1 : index
cf.br ^bb1(%c1_1 : index)
^bb1(%9: index):
@@ -938,7 +938,7 @@ func.func @testupdateop(%a: memref<f32>, %b: memref<f32>, %c: memref<f32>) -> ()
acc.update if(%ifCond) dataOperands(%0: memref<f32>)
acc.update dataOperands(%0: memref<f32>)
acc.update dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>)
- acc.update async() dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>)
+ acc.update async dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>)
acc.update wait dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>)
acc.update dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>) attributes {ifPresent}
return
@@ -957,7 +957,7 @@ func.func @testupdateop(%a: memref<f32>, %b: memref<f32>, %c: memref<f32>) -> ()
// CHECK: acc.update if([[IFCOND]]) dataOperands(%{{.*}} : memref<f32>)
// CHECK: acc.update dataOperands(%{{.*}} : memref<f32>)
// CHECK: acc.update dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>)
-// CHECK: acc.update async() dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>)
+// CHECK: acc.update async dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>)
// CHECK: acc.update wait dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>)
// CHECK: acc.update dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>) attributes {ifPresent}
@@ -1475,7 +1475,7 @@ func.func @acc_reduc_test(%a : i64) -> () {
%c10 = arith.constant 10 : index
%c1 = arith.constant 1 : index
acc.parallel reduction(@reduction_add_i64 -> %a : i64) {
- acc.loop reduction(@reduction_add_i64 -> %a : i64) (%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
+ acc.loop reduction(@reduction_add_i64 -> %a : i64) control(%iv : index) = (%c0 : index) to (%c10 : index) step (%c1 : index) {
acc.yield
} attributes { inclusiveUpperbound = array<i1: true> }
acc.yield
>From a03f709b2532d3e832d5172b8309e9f80d6cdc6a Mon Sep 17 00:00:00 2001
From: Valentin Clement <clementval at gmail.com>
Date: Mon, 5 Feb 2024 14:04:43 -0800
Subject: [PATCH 2/2] Update test
---
mlir/test/Dialect/OpenACC/legalize-data.mlir | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/mlir/test/Dialect/OpenACC/legalize-data.mlir b/mlir/test/Dialect/OpenACC/legalize-data.mlir
index f9857411306c05..4c86223c720a33 100644
--- a/mlir/test/Dialect/OpenACC/legalize-data.mlir
+++ b/mlir/test/Dialect/OpenACC/legalize-data.mlir
@@ -67,7 +67,7 @@ func.func @test(%a: memref<10xf32>) {
%c10 = arith.constant 10 : index
%create = acc.create varPtr(%a : memref<10xf32>) -> memref<10xf32>
acc.parallel dataOperands(%create : memref<10xf32>) {
- acc.loop (%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
+ acc.loop control(%i : index) = (%lb : index) to (%c10 : index) step (%st : index) {
%ci = memref.load %a[%i] : memref<10xf32>
acc.yield
}
@@ -80,7 +80,7 @@ func.func @test(%a: memref<10xf32>) {
// CHECK-SAME: (%[[A:.*]]: memref<10xf32>)
// CHECK: %[[CREATE:.*]] = acc.create varPtr(%[[A]] : memref<10xf32>) -> memref<10xf32>
// CHECK: acc.parallel dataOperands(%[[CREATE]] : memref<10xf32>) {
-// CHECK: acc.loop (%[[I:.*]] : index) = (%{{.*}} : index) to (%{{.*}} : index) step (%{{.*}} : index) {
+// CHECK: acc.loop control(%[[I:.*]] : index) = (%{{.*}} : index) to (%{{.*}} : index) step (%{{.*}} : index) {
// DEVICE: %{{.*}} = memref.load %[[CREATE:.*]][%[[I]]] : memref<10xf32>
// CHECK: acc.yield
// CHECK: }
More information about the flang-commits
mailing list