[flang-commits] [lldb] [compiler-rt] [clang-tools-extra] [llvm] [flang] [clang] [libcxx] [libc] [lld] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

[Philip Reames via flang-commits]

================
@@ -326,6 +326,50 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     switch (Kind) {
     default:
       break;
+    case TTI::SK_ExtractSubvector:
+      if (isa<FixedVectorType>(SubTp)) {
+        unsigned TpRegs = getRegUsageForType(Tp);
+        unsigned NumElems =
+            divideCeil(Tp->getElementCount().getFixedValue(), TpRegs);
+        // Whole vector extract - just the vector itself + (possible) vsetvli.
+        // TODO: consider adding the cost for vsetvli.
+        if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+                           Index % NumElems == 0)) {
+          std::pair<InstructionCost, MVT> SubLT =
+              getTypeLegalizationCost(SubTp);
+          return Index == 0
+                     ? TTI::TCC_Free
+                     : SubLT.first * getRISCVInstructionCost(RISCV::VMV_V_V,
----------------
preames wrote:

For a full VREG case, you never need the VMV_V_V.  You only need the VMV_V_V if NumElems < VLMAX.  

Extending this to sub-register extract with exact VLEN known would be reasonable, but let's do that in a separate patch.

https://github.com/llvm/llvm-project/pull/80164