[flang-commits] [flang] 78a09cb - [mlir][opeancc] Update acc.update verifier for dataOperands

[Valentin Clement via flang-commits]

Author: Valentin Clement
Date: 2023-05-08T09:29:29-07:00
New Revision: 78a09cbd3e2890b5cd03cd66b2cc98d83811a728

URL: https://github.com/llvm/llvm-project/commit/78a09cbd3e2890b5cd03cd66b2cc98d83811a728
DIFF: https://github.com/llvm/llvm-project/commit/78a09cbd3e2890b5cd03cd66b2cc98d83811a728.diff

LOG: [mlir][opeancc] Update acc.update verifier for dataOperands

Data operands associated with acc.update should comes
from acc data entry/exit operations or acc.getdeviceptr.

Reviewed By: razvanlupusoru

Differential Revision: https://reviews.llvm.org/D149990

Added: 
    

Modified: 
    flang/test/Lower/OpenACC/acc-update.f90
    mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
    mlir/test/Dialect/OpenACC/invalid.mlir

Removed: 
    


################################################################################
diff  --git a/flang/test/Lower/OpenACC/acc-update.f90 b/flang/test/Lower/OpenACC/acc-update.f90
index 7456ef62aa1f6..ee02371e2d4f6 100644
--- a/flang/test/Lower/OpenACC/acc-update.f90
+++ b/flang/test/Lower/OpenACC/acc-update.f90
@@ -16,7 +16,6 @@ subroutine acc_update
 ! CHECK: acc.update dataOperands(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>){{$}}
 ! CHECK: acc.update_host accPtr(%[[DEVPTR_A]] : !fir.ref<!fir.array<10x10xf32>>) bounds(%{{.*}}, %{{.*}}) to varPtr(%[[A]] : !fir.ref<!fir.array<10x10xf32>>) {name = "a", structured = false}
 
-
   !$acc update host(a) if(.true.)
 ! CHECK: %[[DEVPTR_A:.*]] = acc.getdeviceptr varPtr(%[[A]] : !fir.ref<!fir.array<10x10xf32>>) bounds(%{{.*}}, %{{.*}}) -> !fir.ref<!fir.array<10x10xf32>> {dataClause = 17 : i64, name = "a", structured = false}
 ! CHECK: %[[IF1:.*]] = arith.constant true

diff  --git a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
index 9c7b56a80a9da..efcc809383da8 100644
--- a/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
+++ b/mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
@@ -655,6 +655,12 @@ LogicalResult acc::UpdateOp::verify() {
   if (getWaitDevnum() && getWaitOperands().empty())
     return emitError("wait_devnum cannot appear without waitOperands");
 
+  for (mlir::Value operand : getDataClauseOperands())
+    if (!mlir::isa<acc::UpdateDeviceOp, acc::UpdateHostOp, acc::GetDevicePtrOp>(
+            operand.getDefiningOp()))
+      return emitError("expect data entry/exit operation or acc.getdeviceptr "
+                       "as defining op");
+
   return success();
 }
 

diff  --git a/mlir/test/Dialect/OpenACC/invalid.mlir b/mlir/test/Dialect/OpenACC/invalid.mlir
index b8b9c30f03129..9c6ec08ca5a23 100644
--- a/mlir/test/Dialect/OpenACC/invalid.mlir
+++ b/mlir/test/Dialect/OpenACC/invalid.mlir
@@ -219,3 +219,8 @@ acc.enter_data dataOperands(%value : memref<10xf32>)
 // expected-error at +1 {{operand #0 must be integer or index, but got 'f32'}}
 %1 = acc.bounds lowerbound(%0 : f32)
 
+// -----
+
+%value = memref.alloc() : memref<10xf32>
+// expected-error at +1 {{expect data entry/exit operation or acc.getdeviceptr as defining op}}
+acc.update dataOperands(%value : memref<10xf32>)