[flang-commits] [flang] [Flang] fix ppc-vec intrinsics testcases on AIX (NFC) (PR #74347)
via flang-commits
flang-commits at lists.llvm.org
Mon Dec 4 09:34:44 PST 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-flang-fir-hlfir
Author: None (madanial0)
<details>
<summary>Changes</summary>
Modify ppc-vec intrinsic test cases to include support for both little and big endianness
---
Patch is 80.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/74347.diff
6 Files Affected:
- (modified) flang/test/Lower/PowerPC/ppc-vec-convert.f90 (+14-10)
- (modified) flang/test/Lower/PowerPC/ppc-vec-extract.f90 (+75-25)
- (modified) flang/test/Lower/PowerPC/ppc-vec-insert.f90 (+74-25)
- (modified) flang/test/Lower/PowerPC/ppc-vec-load.f90 (+44-29)
- (modified) flang/test/Lower/PowerPC/ppc-vec-perm.f90 (+32-21)
- (modified) flang/test/Lower/PowerPC/ppc-vec-splat.f90 (+82-41)
``````````diff
diff --git a/flang/test/Lower/PowerPC/ppc-vec-convert.f90 b/flang/test/Lower/PowerPC/ppc-vec-convert.f90
index 14e247f83df67..0f449a86dbe96 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-convert.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-convert.f90
@@ -1,4 +1,5 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
! REQUIRES: target=powerpc{{.*}}
!---------
@@ -1316,10 +1317,11 @@ subroutine vec_cvf_test_r4r8(arg1)
! LLVMIR: %[[arg:.*]] = load <2 x double>, ptr %{{.*}}, align 16
! LLVMIR: %[[call:.*]] = call contract <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %[[arg]])
-! LLVMIR: %[[b:.*]] = bitcast <4 x float> %[[call]] to <16 x i8>
-! LLVMIR: %[[sh:.*]] = shufflevector <16 x i8> %[[b]], <16 x i8> %[[b]], <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
-! LLVMIR: %[[r:.*]] = bitcast <16 x i8> %[[sh]] to <4 x float>
-! LLVMIR: store <4 x float> %[[r]], ptr %{{.*}}, align 16
+! LLVMIR-LE: %[[b:.*]] = bitcast <4 x float> %[[call]] to <16 x i8>
+! LLVMIR-LE: %[[sh:.*]] = shufflevector <16 x i8> %[[b]], <16 x i8> %[[b]], <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
+! LLVMIR-LE: %[[r:.*]] = bitcast <16 x i8> %[[sh]] to <4 x float>
+! LLVMIR-LE: store <4 x float> %[[r]], ptr %{{.*}}, align 16
+! LLVMIR-BE: store <4 x float> %[[call]], ptr %{{.*}}, align 16
end subroutine vec_cvf_test_r4r8
! CHECK-LABEL: vec_cvf_test_r8r4
@@ -1329,10 +1331,12 @@ subroutine vec_cvf_test_r8r4(arg1)
r = vec_cvf(arg1)
! LLVMIR: %[[arg:.*]] = load <4 x float>, ptr %{{.*}}, align 16
-! LLVMIR: %[[bfi:.*]] = bitcast <4 x float> %[[arg]] to <16 x i8>
-! LLVMIR: %[[sh:.*]] = shufflevector <16 x i8> %[[bfi]], <16 x i8> %[[bfi]], <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
-! LLVMIR: %[[bif:.*]] = bitcast <16 x i8> %[[sh]] to <4 x float>
-! LLVMIR: %[[r:.*]] = call contract <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %[[bif]])
-! LLVMIR: store <2 x double> %[[r]], ptr %{{.*}}, align 16
+! LLVMIR-LE: %[[bfi:.*]] = bitcast <4 x float> %[[arg]] to <16 x i8>
+! LLVMIR-LE: %[[sh:.*]] = shufflevector <16 x i8> %[[bfi]], <16 x i8> %[[bfi]], <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11>
+! LLVMIR-LE: %[[bif:.*]] = bitcast <16 x i8> %[[sh]] to <4 x float>
+! LLVMIR-LE: %[[r:.*]] = call contract <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %[[bif]])
+! LLVMIR-LE: store <2 x double> %[[r]], ptr %{{.*}}, align 16
+! LLVMIR-BE: %[[r:.*]] = call contract <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %[[arg]])
+! LLVMIR-BE: store <2 x double> %[[call]], ptr %{{.*}}, align 16
end subroutine vec_cvf_test_r8r4
diff --git a/flang/test/Lower/PowerPC/ppc-vec-extract.f90 b/flang/test/Lower/PowerPC/ppc-vec-extract.f90
index 1930c8b79d837..0f279347b6b75 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-extract.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-extract.f90
@@ -1,4 +1,5 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
! REQUIRES: target=powerpc{{.*}}
!-------------
@@ -17,7 +18,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i8 %[[s]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
r = vec_extract(x, i2)
@@ -25,7 +28,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i16 %[[s]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
r = vec_extract(x, i4)
@@ -33,7 +38,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i32 %[[s]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
r = vec_extract(x, i8)
@@ -41,7 +48,9 @@ subroutine vec_extract_testf32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i64 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x float> %[[x]], i64 %[[s]]
! LLVMIR: store float %[[r]], ptr %{{[0-9]}}, align 4
end subroutine vec_extract_testf32
@@ -58,7 +67,9 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i8 %[[s]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
r = vec_extract(x, i2)
@@ -66,15 +77,20 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i16 %[[s]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
+
r = vec_extract(x, i4)
! LLVMIR: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i32 %[[s]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
r = vec_extract(x, i8)
@@ -82,7 +98,9 @@ subroutine vec_extract_testf64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i64 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x double> %[[x]], i64 %[[s]]
! LLVMIR: store double %[[r]], ptr %{{[0-9]}}, align 8
end subroutine vec_extract_testf64
@@ -99,7 +117,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 16
-! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 15, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i8 %[[s]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
r = vec_extract(x, i2)
@@ -107,7 +127,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 16
-! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 15, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i16 %[[s]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
r = vec_extract(x, i4)
@@ -115,7 +137,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 16
-! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 15, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i32 %[[s]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
r = vec_extract(x, i8)
@@ -123,7 +147,9 @@ subroutine vec_extract_testi8(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 16
-! LLVMIR: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i64 15, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <16 x i8> %[[x]], i64 %[[s]]
! LLVMIR: store i8 %[[r]], ptr %{{[0-9]}}, align 1
end subroutine vec_extract_testi8
@@ -140,7 +166,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 8
-! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 7, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i8 %[[s]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
r = vec_extract(x, i2)
@@ -148,7 +176,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 8
-! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 7, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i16 %[[s]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
r = vec_extract(x, i4)
@@ -156,7 +186,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 8
-! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 7, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i32 %[[s]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
r = vec_extract(x, i8)
@@ -164,7 +196,9 @@ subroutine vec_extract_testi16(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 8
-! LLVMIR: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i64 7, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <8 x i16> %[[x]], i64 %[[s]]
! LLVMIR: store i16 %[[r]], ptr %{{[0-9]}}, align 2
end subroutine vec_extract_testi16
@@ -181,7 +215,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i8 %[[s]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
r = vec_extract(x, i2)
@@ -189,7 +225,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i16 %[[s]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
r = vec_extract(x, i4)
@@ -197,7 +235,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i32 %[[s]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
r = vec_extract(x, i8)
@@ -205,7 +245,9 @@ subroutine vec_extract_testi32(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 4
-! LLVMIR: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i64 3, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <4 x i32> %[[x]], i64 %[[s]]
! LLVMIR: store i32 %[[r]], ptr %{{[0-9]}}, align 4
end subroutine vec_extract_testi32
@@ -222,7 +264,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[u:.*]] = urem i8 %[[i1]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i8 %[[s]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
r = vec_extract(x, i2)
@@ -230,7 +274,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[u:.*]] = urem i16 %[[i2]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i16 %[[s]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
r = vec_extract(x, i4)
@@ -238,7 +284,9 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[u:.*]] = urem i32 %[[i4]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i32 %[[s]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
r = vec_extract(x, i8)
@@ -246,6 +294,8 @@ subroutine vec_extract_testi64(x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[u:.*]] = urem i64 %[[i8]], 2
-! LLVMIR: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[s:.*]] = sub i64 1, %[[u]]
+! LLVMIR-LE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[u]]
+! LLVMIR-BE: %[[r:.*]] = extractelement <2 x i64> %[[x]], i64 %[[s]]
! LLVMIR: store i64 %[[r]], ptr %{{[0-9]}}, align 8
end subroutine vec_extract_testi64
diff --git a/flang/test/Lower/PowerPC/ppc-vec-insert.f90 b/flang/test/Lower/PowerPC/ppc-vec-insert.f90
index 3648be6ac027e..dd57fcc67be08 100644
--- a/flang/test/Lower/PowerPC/ppc-vec-insert.f90
+++ b/flang/test/Lower/PowerPC/ppc-vec-insert.f90
@@ -1,4 +1,5 @@
-! RUN: %flang_fc1 -flang-experimental-hlfir -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR" %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-LE" %s
+! RUN: %flang_fc1 -flang-experimental-hlfir -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefixes="LLVMIR","LLVMIR-BE" %s
! REQUIRES: target=powerpc{{.*}}
! vec_insert
@@ -18,7 +19,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i1:.*]] = load i8, ptr %{{[0-9]}}, align 1
! LLVMIR: %[[urem:.*]] = urem i8 %[[i1]], 4
-! LLVMIR: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i8 %[[urem]]
+! LLVMIR-BE: %[[s:.*]] = sub i8 3, %[[urem]]
+! LLVMIR-LE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i8 %[[urem]]
+! LLVMIR-BE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i8 %[[s]]
! LLVMIR: store <4 x float> %[[r]], ptr %{{[0-9]}}, align 16
r = vec_insert(v, x, i2)
@@ -27,7 +30,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i2:.*]] = load i16, ptr %{{[0-9]}}, align 2
! LLVMIR: %[[urem:.*]] = urem i16 %[[i2]], 4
-! LLVMIR: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i16 %[[urem]]
+! LLVMIR-BE: %[[s:.*]] = sub i16 3, %[[urem]]
+! LLVMIR-LE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i16 %[[urem]]
+! LLVMIR-BE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i16 %[[s]]
! LLVMIR: store <4 x float> %[[r]], ptr %{{[0-9]}}, align 16
r = vec_insert(v, x, i4)
@@ -36,7 +41,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i4:.*]] = load i32, ptr %{{[0-9]}}, align 4
! LLVMIR: %[[urem:.*]] = urem i32 %[[i4]], 4
-! LLVMIR: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i32 %[[urem]]
+! LLVMIR-BE: %[[s:.*]] = sub i32 3, %[[urem]]
+! LLVMIR-LE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i32 %[[urem]]
+! LLVMIR-BE: %[[r:.*]] = insertelement <4 x float> %[[x]], float %[[v]], i32 %[[s]]
! LLVMIR: store <4 x float> %[[r]], ptr %{{[0-9]}}, align 16
r = vec_insert(v, x, i8)
@@ -45,7 +52,9 @@ subroutine vec_insert_testf32(v, x, i1, i2, i4, i8)
! LLVMIR: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
! LLVMIR: %[[i8:.*]] = load i64, ptr %{{[0-9]}}, align 8
! LLVMIR: %[[urem:.*]] = urem i64 %[[i8]], 4
-! LL...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/74347
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