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<p>Fair warning, I'm answering a bit outside my comfort zone, so
some of this might be wrong...</p>
<p>If you're wanting to have an LLVM backend that targets this
abstract machine, then lowering fixed precision integers into
infinite precision integers is fairly straight forward. You just
need to manually implement the twos complement wrapping behaviors
in the integer space w/branching. That probably won't be the
fastest thing in the world, but if you're targeting anything other
than an mature VM, you shouldn't care. <br>
</p>
<p>Your challenge will be representing the infinite integer type in
the backend. You shouldn't need to change IR at all. <br>
</p>
<p>The simplest, and slowest, approach would be to custom lower to a
set of intrinsic calls. If you type your "registers" as oddly
sized pointers into a special address space, you can probably get
that working. Your real challenge will be representing your
"integer store" memory since it is by definition not byte
addressable. I don't really have any good suggestions there. I'd
strongly suggest figuring this piece out before moving on to
anything else.<br>
</p>
<p>The harder approach to the lowering would be introducing an
integer type in into the backend. I have no input on difficulty
of that, other than to say it's probably not worth doing unless
you're pushing performance fairly hard. (I doubt you are.)</p>
<p>Philip<br>
</p>
<div class="moz-cite-prefix">On 11/7/19 9:41 AM, Levi Aul via
cfe-dev wrote:<br>
</div>
<blockquote type="cite"
cite="mid:CAMFocdCobdyQ2F6Vf6ujobSyb+A7y_YjD_ReZVBZ7MLpzKByew@mail.gmail.com">
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<div dir="ltr">Hi, I'm considering writing an LLVM backend to
target an abstract machine, encoding to a bytecode ISA.
<div><br>
</div>
<div>This abstract machine has integers, but not in the sense of
having fixed-size machine words; rather, each abstract-machine
register and memory location can losslessly hold onto a
distinct (non-aliasing) unlimited bit-width value, and
math/bitwise ops will operate losslessly on these values to
produce new values of unlimited bit-width, without any need
for overflow into neighbouring registers/memory locations.</div>
<div><br>
</div>
<div>A VM implementing this abstract machine would, of course,
use some kind of bignum library to implement these
semantics, with each such integer value actually being a
pointer to a VM-heap-allocated bignum; or, perhaps, the VM
would do load-time optimization to strength-reduce some of the
bignums to regular host-CPU integer types.</div>
<div><br>
</div>
<div>But, from the perspective of a compiler targeting the
abstract machine itself, the ISA just "has" registers and ops
of an 'iUNLIMITED' type.</div>
<div><br>
</div>
<div>Does LLVM, and specifically the LLVM IR type system,
support anything like this? If not, would it be the work of
days, or of months, to make it happen?</div>
</div>
<br>
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