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<p class="MsoNormal">> TL;DR: what are these _iso_ things?</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">They are volatile ops that are guaranteed to use 1 instruction to do that load. So for x86 that means using x87, or MMX, or SSE to do the load. They also suppress the ‘volatile is affected by the /volatile:ms vs. /volatile:iso setting’
warnings. <atomic> uses these in conjunction with barrier instrinsics.</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">#if defined(_M_ARM) || defined(_M_ARM64)</p>
<p class="MsoNormal">#define _Memory_barrier() __dmb(0xB) // inner shared data memory barrier</p>
<p class="MsoNormal">#define _Compiler_or_memory_barrier() _Memory_barrier()</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE8(_Storage, _Value) __iso_volatile_store8(_Atomic_address_as<char>(_Storage), _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE16(_Storage, _Value) __iso_volatile_store16(_Atomic_address_as<short>(_Storage), _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE32(_Storage, _Value) __iso_volatile_store32(_Atomic_address_as<int>(_Storage), _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE64(_Storage, _Value) __iso_volatile_store64(_Atomic_address_as<long long>(_Storage), _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_LOAD8(_Storage) __iso_volatile_load8(_Atomic_address_as<const char>(_Storage))</p>
<p class="MsoNormal">#define _ISO_VOLATILE_LOAD16(_Storage) __iso_volatile_load16(_Atomic_address_as<const short>(_Storage))</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">#elif defined(_M_IX86) || defined(_M_X64)</p>
<p class="MsoNormal">// x86/x64 hardware only emits memory barriers inside _Interlocked intrinsics</p>
<p class="MsoNormal">#define _Compiler_or_memory_barrier() _Compiler_barrier()</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE8(_Storage, _Value) (*_Atomic_address_as<char>(_Storage) = _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE16(_Storage, _Value) (*_Atomic_address_as<short>(_Storage) = _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE32(_Storage, _Value) (*_Atomic_address_as<long>(_Storage) = _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_STORE64(_Storage, _Value) (*_Atomic_address_as<long long>(_Storage) = _Value)</p>
<p class="MsoNormal">#define _ISO_VOLATILE_LOAD8(_Storage) (*_Atomic_address_as<const char>(_Storage))</p>
<p class="MsoNormal">#define _ISO_VOLATILE_LOAD16(_Storage) (*_Atomic_address_as<const short>(_Storage))</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">#else // ^^^ x86/x64 / unsupported hardware vvv</p>
<p class="MsoNormal">#error Unsupported hardware</p>
<p class="MsoNormal">#endif // hardware</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">…. Later…</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">// in _<i>Atomic</i>_storage<1></p>
<p class="MsoNormal"> _NODISCARD _Ty load() const noexcept { // load with sequential consistency</p>
<p class="MsoNormal"> char _As_bytes = _ISO_VOLATILE_LOAD8(_Storage);</p>
<p class="MsoNormal"> _Compiler_or_memory_barrier();</p>
<p class="MsoNormal"> return reinterpret_cast<_Ty&>(_As_bytes);</p>
<p class="MsoNormal"> }</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"> _NODISCARD _Ty load(const memory_order _Order) const noexcept { // load with given memory order</p>
<p class="MsoNormal"> char _As_bytes = _ISO_VOLATILE_LOAD8(_Storage);</p>
<p class="MsoNormal"> _Load_barrier(_Order);</p>
<p class="MsoNormal"> return reinterpret_cast<_Ty&>(_As_bytes);</p>
<p class="MsoNormal"> }</p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Billy3</p>
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<p class="MsoNormal" style="border:none;padding:0in"><b>From: </b><a href="mailto:jfbastien@apple.com">JF Bastien</a><br>
<b>Sent: </b>Tuesday, July 30, 2019 8:43 PM<br>
<b>To: </b><a href="mailto:efriedma@quicinc.com">Eli Friedman</a><br>
<b>Cc: </b><a href="mailto:rnk@google.com">rnk@google.com</a>; <a href="mailto:bion@microsoft.com">
Billy O'Neal (VC LIBS)</a>; <a href="mailto:cfe-dev@lists.llvm.org">cfe-dev</a><br>
<b>Subject: </b>Re: [cfe-dev] FYI, Intel folks might be looking to add the __iso_volatile_Xxx family for MSVC STL <atomic> soon</p>
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<p class="MsoNormal">On Jul 30, 2019, at 5:21 PM, Eli Friedman via cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org">cfe-dev@lists.llvm.org</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b><span class="apple-converted-space"> </span>cfe-dev <<a href="mailto:cfe-dev-bounces@lists.llvm.org"><span style="color:purple">cfe-dev-bounces@lists.llvm.org</span></a>><span class="apple-converted-space"> </span><b>On Behalf
Of<span class="apple-converted-space"> </span></b>Reid Kleckner via cfe-dev<br>
<b>Sent:</b><span class="apple-converted-space"> </span>Tuesday, July 30, 2019 4:54 PM<br>
<b>To:</b><span class="apple-converted-space"> </span>Billy O'Neal (VC LIBS) <<a href="mailto:bion@microsoft.com"><span style="color:purple">bion@microsoft.com</span></a>><br>
<b>Cc:</b><span class="apple-converted-space"> </span>cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org"><span style="color:purple">cfe-dev@lists.llvm.org</span></a>><br>
<b>Subject:</b><span class="apple-converted-space"> </span>[EXT] Re: [cfe-dev] FYI, Intel folks might be looking to add the __iso_volatile_Xxx family for MSVC STL <atomic> soon<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">On Tue, Jul 30, 2019 at 4:15 PM Billy O'Neal (VC LIBS) <<a href="mailto:bion@microsoft.com"><span style="color:purple">bion@microsoft.com</span></a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal">> we can worry about optimization, perhaps using _Atomic, later<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">We can’t use _Atomic because it would not be ABI compatible with our std::atomic; in particular, because we put the spinlock for non-lock-free atomics inside the atomic, for instance. And because that isn’t a thing for some of our supported
frontends.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">It is possible that there are different intrinsics we could call for Clang that would make you folks happier, but we don’t know what those are or even if they exist at present.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">I was thinking that perhaps the _Atomic_address_as template would do the necessary casts to use it when necessary without changing the storage type inside the std::atomic object.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">There are actually multiple APIs to access C++11 atomics in clang, since we invented APIs in parallel with gcc. The __atomic_* builtins (<a href="https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgcc.gnu.org%2Fonlinedocs%2Fgcc%2F_005f_005fatomic-Builtins.html&data=02%7C01%7Cbion%40microsoft.com%7C320671f55ce84bdf39b608d715694efa%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637001414353321850&sdata=CZx0Rk17szgX9vvi%2BPqV3%2Fu7aTr8IBjUKvhYKFVZlVM%3D&reserved=0"><span style="color:purple">https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html</span></a>)
don’t require the use of _Atomic types.<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal">Using volatile loads and stores with barriers probably prevents the compiler from performing any breaking optimizations, assuming the RMW atomics are protected appropriately, and the user doesn’t call any of the clang atomic builtins directly.
But it’s not a good idea; it won’t optimize well. For example, on AArch64, it will prevent the compiler from using the dedicated load-acquire and store-release instructions.<o:p></o:p></p>
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<p class="MsoNormal">TL;DR: what are these _iso_ things? I read the bug report, I don’t see the details I’d expect.<o:p></o:p></p>
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<p class="MsoNormal">I think the __atomic_* builtins should work as Eli suggests.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">-Eli<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif">_______________________________________________<br>
cfe-dev mailing list<br>
</span><a href="mailto:cfe-dev@lists.llvm.org"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif;color:purple">cfe-dev@lists.llvm.org</span></a><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif"><br>
</span><a href="https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.llvm.org%2Fcgi-bin%2Fmailman%2Flistinfo%2Fcfe-dev&data=02%7C01%7Cbion%40microsoft.com%7C320671f55ce84bdf39b608d715694efa%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C637001414353331848&sdata=PRd3coUtU2EoguRUA8veBImWcmnGW2F0dLWdo1PKzn0%3D&reserved=0"><span style="font-size:9.0pt;font-family:"Helvetica",sans-serif;color:purple">https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev</span></a><o:p></o:p></p>
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