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><span style="font-family: "Segoe UI", "Segoe UI Web (West European)", "Segoe UI", -apple-system, BlinkMacSystemFont, Roboto, "Helvetica Neue", sans-serif; font-size: 15px; background-color: rgb(255, 255, 255); display: inline !important">The optimizers may
change the order of volatile operations relative to non-volatile operations. This is not Java’s “volatile” and has no cross-thread synchronization behavior.</span></div>
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Right, but if they want to link with MSVC++ generated code they need to at least respect
<a href="https://docs.microsoft.com/en-us/cpp/intrinsics/readwritebarrier?view=vs-2017" title="https://docs.microsoft.com/en-us/cpp/intrinsics/readwritebarrier?view=vs-2017">
_ReadWriteBarrier</a>.</div>
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I can certainly mess with our <atomic> to play more nicely with you folks if you want us calling different builtins instead. <atomic> is entirely library tech for us.</div>
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Billy3</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Reid Kleckner <rnk@google.com><br>
<b>Sent:</b> Thursday, March 28, 2019 03:08 PM<br>
<b>To:</b> Billy O'Neal (VC LIBS); Friedman, Eli; Grang, Mandeep Singh<br>
<b>Cc:</b> JF Bastien; cfe-dev<br>
<b>Subject:</b> Re: [cfe-dev] FYI, Intel folks might be looking to add the __iso_volatile_Xxx family for MSVC STL <atomic> soon</font>
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<div dir="ltr">On Thu, Mar 28, 2019 at 2:28 PM Billy O'Neal (VC LIBS) <<a href="mailto:bion@microsoft.com" target="_blank">bion@microsoft.com</a>> wrote:<br>
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><span style="font-size:15px; background-color:rgb(255,255,255); display:inline">Are you sure we shouldn't be marking these as atomic instead of volatile? Volatile is usually not suitable for anything except </span></div>
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I am implementing <atomic> <span id="x_gmail-m_6745075332462224179gmail-m_-3577172427236293292gmail-m_-2703270842879295710🙂" title=":slight_smile:">
🙂</span></div>
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<div>My concern is that volatile in LLVM has nothing to do with atomicity, and I think what you really want is LLVM atomic loads and stores, with real ordering markers of monotonic, seq_cst, release, acquire, etc. This is all described here:</div>
<div><a href="https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fllvm.org%2Fdocs%2FLangRef.html%23volatile-memory-accesses&data=02%7C01%7Cbion%40microsoft.com%7Cd5b30d145383489891e408d6b3ca007c%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C636894077507135048&sdata=73J4avlu9DO5KGNF%2BONhLJVMzl1Z%2F0TMDnJE9fpUkmY%3D&reserved=0" originalsrc="https://llvm.org/docs/LangRef.html#volatile-memory-accesses" shash="kWawVUJRXJEEvUBqJ7PcBwF53MtH/ZrwLnd0QLJ9qRvN1DxmnoDGB/CSYAxIZcUEqZNQD/QF221FwATZvT4/f8BvKbAOjcKR8R33Yq/IP1Bn6yaZoxYH5ow4VPWUuOKvlwJU6ad37oSjdwxNJ+tYK/hFZ6KdSzpWwRBSGKH0di0=" target="_blank">https://llvm.org/docs/LangRef.html#volatile-memory-accesses</a> </div>
<div><a href="https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fllvm.org%2Fdocs%2FLangRef.html%23memory-model-for-concurrent-operations&data=02%7C01%7Cbion%40microsoft.com%7Cd5b30d145383489891e408d6b3ca007c%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C636894077507145039&sdata=Vn1qu6pXuqVPMWJtclPUeFOYp5eK4aLRf2WWJxpzEfA%3D&reserved=0" originalsrc="https://llvm.org/docs/LangRef.html#memory-model-for-concurrent-operations" shash="se//PWiQxJ4oehDEv7yTPM56D2mq3T8vnHbKtb/Xbzt0KH5RGDMfATJS1E+e6gQUAJvyfUy1MrEJ3mm/m2fvgD5oj66/5vno95enDfHxsXN//khkRq5aMCJcddRKaowUGQ7db2pSSF673mn53HTadi8srZrDqm2p9yCYpB4aKf4=" target="_blank">https://llvm.org/docs/LangRef.html#memory-model-for-concurrent-operations</a></div>
<div>In particular: "The optimizers may change the order of volatile operations relative to non-volatile operations. This is not Java’s “volatile” and has no cross-thread synchronization behavior."</div>
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<div>So, I'm concerned that there is something subtly incorrect about using __iso_volatile_* to implement atomics. <br>
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<div>After looking at the xatomic.h source, I think I have a better understanding of what is going on. I added some folks who probably have a better understanding of LLVM IR atomics, and maybe they can help guide the discussion to a simpler implementation of
Visual C++ <atomic> that plays well with LLVM. We had a similar discussion about over- or under-emitting dmb fences in this code review: <a href="https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Freviews.llvm.org%2FD52807&data=02%7C01%7Cbion%40microsoft.com%7Cd5b30d145383489891e408d6b3ca007c%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C636894077507145039&sdata=RroXJ2BBZBaTokulSxd2PTOUor6e56Gm0ii%2Bau9om%2Bw%3D&reserved=0" originalsrc="https://reviews.llvm.org/D52807" shash="abH9BA9SL4YGRb1ksWkM8qOz9ysFN0A6aoUnbs9JZXdJb/ipMH6y/fh3Zj+Ro7BuTEsNmkqvABLke88/7aJuFmhyzGEtxeom8sqoEcXc1GHZc75cbZVOH3Bxh7ye+SLTuNZTDNMmrhDKz0i+x1bMiOAtai+4yil3gPLvQvCWr1w=">https://reviews.llvm.org/D52807</a>.</div>
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<div>The Visual C++ headers currently add fences for ARM themselves. The code looks like this: <a href="https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Freviews.llvm.org%2FP8137&data=02%7C01%7Cbion%40microsoft.com%7Cd5b30d145383489891e408d6b3ca007c%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C636894077507155032&sdata=UORTGrVnJ%2F8IcsoG1Bezaov2sSB7WrXejzHGyCTH4Cc%3D&reserved=0" originalsrc="https://reviews.llvm.org/P8137" shash="WqzNTiQU/KktJGiAHwed9aZEJvILG6AFi0JF+aJVxLv1J01bGLBoCBECX434/mc8NW9tUZ6O12u1qRGfop/wWstyJ60wNLIZAUdjDt0ogmfj6cU1GgufxqgSnRjFB/LFnkzre8nxJKLvSsp8E/ih5UDqiSBCqcrJLu9dGt03rmM=" target="_blank">https://reviews.llvm.org/P8137</a> In
small test cases, this generates the appropriate code, a single load followed by a fence.</div>
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<div>Completely aside from improving the implementation of <atomic> with clang, I will go ahead and make those __iso_volatile_* intrinsics available everywhere.</div>
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