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</o:shapelayout></xml><![endif]--></head><body lang=EN-IE link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>No rush on an answer James I won’t get a chance to follow up on this for a couple of weeks anyway, so enjoy your vacation.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>I think that we have the TTI correct, but there are other problems. For instance ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>getNumberRegisters(true)</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’ is awkward because we have both 32-bit SIMD and 128-bit SIMD registers. Similarly ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>getRegisterBitWidth(true)</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’. We just return ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>32</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’ and ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>128</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’ respectively, because the TTI interface does not allow us to discriminate for 32-bit versus 128-bit vectors.<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>The other hooks are for costs, and for the most part they look reasonable, though I delegate to the ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>BasicTTIImpl</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’ implementation for the interleaved memory cost because I have not yet measured the impact of changing this. Is there any particular cost hook that is more likely than another to influence ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>truncateToMinimalBitwidths</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’?<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>Regarding:<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal style='margin-left:36.0pt'>Both of these should be kicking in already if your target advertises i8 as being legal for scalars or vectors<span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>I am only aware of the DataLayout ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>-n8:16:32</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’ for this, is there an equivalent for vectors? I also have ‘</span><span style='font-family:"Courier New";color:black;mso-fareast-language:EN-US'>-v16:16-v32:32-v128:64</span><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>’, but these only deal with the aggregate size of the vector and not it’s element type. Am I missing a hook in the TTI or STI perhaps?<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'> MartinO<o:p></o:p></span></p><p class=MsoNormal><span style='font-family:"Book Antiqua","serif";color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> James Molloy [mailto:james@jamesmolloy.co.uk] <br><b>Sent:</b> 30 May 2016 21:06<br><b>To:</b> Norman Rink; Martin J. O'Riordan; David Majnemer; Dilan Manatunga<br><b>Cc:</b> Clang Dev<br><b>Subject:</b> Re: [cfe-dev] Disable integer promotion (Dilan Manatunga via cfe-dev)<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi,<br><br>I'm on vacation at the moment with only a phone to reply on but...<br><br>TruncateToMinimalBitwidths is, as you point out, only for vectorisation. There are three cases:<br><br>1. I8 and i16 are never supported on the target. <br>2. I8 and i16 are supported for vectors but not for scalars (ARM)<br>3. I8 and i16 are supported for scalars and vectors (x86)<br><br>(3) is handled by simplifyDemandedBits in the instruction combiner, so it will work on scalars and vectors but will only ever truncate promotions if the smaller integer operation is valid on the target. <br><br>(2) is handled by truncateToMinimalBitwidths where we need to, as part of the vectorisation profitability analysis, determine what the loop will look like after vectorisation. We insert trunc and ext nodes simply as a shortcut - we could elide the promotions as you do, but there are corner cases that make it a bit awkward so we just add more casts and let a cleanup pass (instcombine) remove them intelligently. <br><br>I hope this answers your queries a bit more? Both of these should be kicking in already if your target advertises i8 as being legal for scalars or vectors, so I would check your target transform info to ensure the legality hook is returning true when it should. <br><br>Cheers <br><br>James <o:p></o:p></p><div><div><p class=MsoNormal>On Mon, 30 May 2016 at 16:11, Norman Rink <<a href="mailto:norman.rink@tu-dresden.de">norman.rink@tu-dresden.de</a>> wrote:<o:p></o:p></p></div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm'><div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'>Hi all,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'>I realize this is potentially only tangent to the ongoing discussion, but does anyone have significant experience with how integer promotion interacts with vectorization? When I looked into this interaction, I did not have the time to conduct a careful analysis, but I have reason to believe that integer promotion can get in the way of vectorization, thereby limiting its benefits. Can anyone comment? Thanks.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'>Best,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'>Norman<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p></div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:black'>From: </span></b><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:black'>"Martin J. O'Riordan" <<a href="mailto:martin.oriordan@movidius.com" target="_blank">martin.oriordan@movidius.com</a>><br><b>Organization: </b>Movidius Ltd.<br><b>Date: </b>Monday 30 May 2016 14:53<br><b>To: </b>'James Molloy' <<a href="mailto:james@jamesmolloy.co.uk" target="_blank">james@jamesmolloy.co.uk</a>>, 'David Majnemer' <<a href="mailto:david.majnemer@gmail.com" target="_blank">david.majnemer@gmail.com</a>>, 'Dilan Manatunga' <<a href="mailto:manatunga@gmail.com" target="_blank">manatunga@gmail.com</a>><br><b>Cc: </b>'Clang Dev' <<a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a>>, Norman Rink <<a href="mailto:norman.rink@tu-dresden.de" target="_blank">norman.rink@tu-dresden.de</a>><br><b>Subject: </b>RE: [cfe-dev] Disable integer promotion (Dilan Manatunga via cfe-dev)<o:p></o:p></span></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.5pt;font-family:"Calibri","sans-serif";color:black'><o:p> </o:p></span></p></div><div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>Hi James and thanks for pointing out the existence of this transformation, we were quite unaware of it.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>As it happens, I am highly allergic to re-invention and avoid doing so whenever possible; the only reason an already overburdened team of 2 developers will re-invent is because they are unaware of an existing solution which is not difficult given the scope and complexity of LLVM.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>So far as I can tell, ‘</span><span style='font-family:"Courier New";color:black'>truncateToMinimalBitwidths</span><span style='font-family:"Book Antiqua","serif";color:#1F497D'>’ is always enabled, so it is not a target specific selection and our target should automatically reap the rewards of this optimisation pass. I certainly cannot find a switch to enable or disable it. But in fact we are not seeing anywhere near the benefits we would expect.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:36.0pt'><span style='font-family:"Courier New";color:black'>void InnerLoopVectorizer::truncateToMinimalBitwidths() {</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:36.0pt'><span style='font-family:"Courier New";color:black'> // For every instruction `I` in MinBWs, truncate the operands, create a</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:36.0pt'><span style='font-family:"Courier New";color:black'> // truncated version of `I` and reextend its result. InstCombine runs</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto;margin-left:36.0pt'><span style='font-family:"Courier New";color:black'> // later and will remove any ext/trunc pairs.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>This appears to only run on inner-loops, and it appear to insert narrowings/truncations and subsequent widenings/extendings into the IR chains.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>The DataLayout for our target includes “</span><span style='font-family:"Courier New";color:black'>-n8:16:32</span><span style='font-family:"Book Antiqua","serif";color:#1F497D'>”, so it should see the benefits of optimisations for multiple native integer support. We also provide both 32-bit SIMD and 128-bit SIMD native support.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>The pass that we wrote is quite different. It is run as a machine pass prior to loop-unrolling and vectorisation, and instead of pre-truncating and post-extending IR chains, it removes the existing pre-extending and post-truncating that brackets a sequence of IR operations if it can prove that the outcome is the same. The results are actually very good and match what our expectations are from such a transformation, which makes me wonder “why does ‘</span><span style='font-family:"Courier New";color:black'>truncateToMinimalBitwidths</span><span style='font-family:"Book Antiqua","serif";color:#1F497D'>’ not already produce comparable results?”.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>Our observations are that with the new pass, a significant majority of vectorised code showed some improvement, with results as high as 40X faster than without. Of the small number of tests that regressed in performance, adding a ‘</span><span style='font-family:"Courier New";color:black'>#pragma clang unroll_count(N)</span><span style='font-family:"Book Antiqua","serif";color:#1F497D'>’ eliminated the loss. This could probably be eliminate too by better tuning of the cost-models.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>The re-invention is inadvertent, but in any event our new pass appears to provide considerable additional performance improvements that are not currently happening with the stock LLVM transformations.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'>I will have to contrive some tests to see why ‘</span><span style='font-family:"Courier New";color:black'>truncateToMinimalBitwidths</span><span style='font-family:"Book Antiqua","serif";color:#1F497D'>’ is not already doing this, and if there is something that we have done wrong in our target that is breaking it, I will happily revert to an existing solution.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> MartinO</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#1F497D'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:black'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:black'> James Molloy [<a href="mailto:james@jamesmolloy.co.uk" target="_blank">mailto:james@jamesmolloy.co.uk</a>] <br><b>Sent:</b> 28 May 2016 19:58<br><b>To:</b> <a href="mailto:Martin.ORiordan@movidius.com" target="_blank">Martin.ORiordan@movidius.com</a>; David Majnemer; Dilan Manatunga<br><b>Cc:</b> Clang Dev; Norman Rink<br><b>Subject:</b> Re: [cfe-dev] Disable integer promotion (Dilan Manatunga via cfe-dev)</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'> <o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>Hi,<br><br>X86 has native support for i8 and i16. Aarch64 and ARM have native i8 and i16 vector operations that are lowered and analysed using truncateToMinimalBitwidths in LoopVectorize. Similarly for scalar code on x86 truncation is done in instcombine. <br><br>Why do you need to reinvent this?<br><br>Cheers,<br><br>James<o:p></o:p></span></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>On Sat, 28 May 2016 at 19:02, Martin J. O'Riordan via cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a>> wrote:<o:p></o:p></span></p></div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0cm;margin-bottom:5.0pt'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'>Instead of suppressing the integer promotion rules which are part of the ISO C/C++ Standards, we wrote a new pass that analyses the IR to see if the input values and output value were of an integer type that was narrower than the promoted types used in the IR, and if we could prove that the outcome would be identical if the type was unpromoted, then we reduced the IR to use the narrower form.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'>In our case the motive was to enhance vectorisation because our vector ALU can work with 8-, 16- and 32-bit integers natively, and handling ‘</span><span style='font-family:"Courier New";color:black'>vXi8</span><span style='font-family:"Book Antiqua","serif";color:#943634'>’ vectors ended was actually being promoted to multiple ‘</span><span style='font-family:"Courier New";color:black'>v4i32</span><span style='font-family:"Book Antiqua","serif";color:#943634'>’ vectors requiring 4 times as many instructions as were necessary, or worse still, fully scalarized.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'>This pass was presented by my colleague Stephen Rogers in a “Lighting Talk” at the October 2015 LLVM Conference in San Jose and titled “</span><span style='font-family:"Book Antiqua","serif";color:black'>Integer Vector Optimizations and “Usual Arithmetic Conversions”</span><span style='font-family:"Book Antiqua","serif";color:#943634'>”. I can’t find the paper or slides on the LLVM Meetings page, perhaps these are not archived for Lightning Talks (?), but as they are not large I have attached them here.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'>This approach allowed us to gain the optimisations that are possible with our architecture which supports 8-, 16- and 32-bit native integer computations (scalar and vector), while also respecting the ISO C and C++ Standards. I am a lot more nervous of a front-end switch for this, as it will lead to non-compliant programs, and in the presence of overloading and template-instantiation it could also lead to very different programs, and would recommend that we do not add a front-end switch which alters the semantics of the language in this way.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'>It is my intention to publish this pass if it is of general interest, and since it is target independent there are no particular blocking issue for me (Patents, IP, etc.) to doing so. I do have to catch-up on the HEAD revision to ensure that it still works correctly, but it was working perfectly at SVN #262824 and it will be a month before I have enough time to catch up on the HEAD revision as we are busy with a product release that takes precedence.</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'>All the best,</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> MartinO</span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-family:"Book Antiqua","serif";color:#943634'> </span><span style='color:black'><o:p></o:p></span></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:black'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:black'> cfe-dev [mailto:<a href="mailto:cfe-dev-bounces@lists.llvm.org" target="_blank">cfe-dev-bounces@lists.llvm.org</a>] <b>On Behalf Of </b>David Majnemer via cfe-dev<br><b>Sent:</b> 27 May 2016 19:55<br><b>To:</b> Dilan Manatunga <<a href="mailto:manatunga@gmail.com" target="_blank">manatunga@gmail.com</a>><br><b>Cc:</b> clang developer list <<a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a>>; Norman Rink <<a href="mailto:norman.rink@tu-dresden.de" target="_blank">norman.rink@tu-dresden.de</a>>; <a href="mailto:cfe-dev-request@lists.llvm.org" target="_blank">cfe-dev-request@lists.llvm.org</a><br><b>Subject:</b> Re: [cfe-dev] Disable integer promotion (Dilan Manatunga via cfe-dev)</span><span style='color:black'><o:p></o:p></span></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'> <o:p></o:p></span></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>You could set IntWidth to 16 or 8 in clang, not unlike what MSP430 does:<o:p></o:p></span></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'><a href="https://github.com/llvm-mirror/clang/blob/3317d0fa0bd1f5c5adc14bcc6adc2a38acc9064b/lib/Basic/Targets.cpp#L6823" target="_blank">https://github.com/llvm-mirror/clang/blob/3317d0fa0bd1f5c5adc14bcc6adc2a38acc9064b/lib/Basic/Targets.cpp#L6823</a><o:p></o:p></span></p></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'> <o:p></o:p></span></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>On Fri, May 27, 2016 at 10:32 AM, Dilan Manatunga via cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a>> wrote:<o:p></o:p></span></p><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0cm;margin-bottom:5.0pt'><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>I need disabling this feature because I am researching architectures where 8-bit or 16-bit adds are preferred to 32-bit. So, integer promotion kinda mucks everything up. I was hoping there was a way in clang to disable it, instead of having to implement an LLVM pass to coalesce unnecessary promotions. <o:p></o:p></span></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'> <o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>Thanks for catching the IR mistake. Should have double checked that. This should be the correct version:<o:p></o:p></span></p></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>nt8_t a = 1;</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>int8_t b = 2;</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>int8_t c = a + b</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'> </span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>The LLVM IR will be:</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>%x = sext i8 %a to i32</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>%y = sext i8 %b to i32</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>%z = add nsw i32 %x, %y</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>%c = trunc i32 %z to i8</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'> </span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>Instead, it would simply compile to:</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>$c = add nsw i8 %z, $y</span><span style='color:black'><o:p></o:p></span></p></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'> </span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'>-Dilan</span><span style='color:black'><o:p></o:p></span></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.0pt;font-family:"Verdana","sans-serif";color:black'> </span><span style='color:black'><o:p></o:p></span></p></div></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'> <o:p></o:p></span></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>On Fri, May 27, 2016 at 5:30 AM Norman Rink via cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a>> wrote:<o:p></o:p></span></p></div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-top:5.0pt;margin-right:0cm;margin-bottom:5.0pt'><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>Hi Dilan,<br><br>I would like to second your request for an option to disable integer<br>promotion. What do you need it for?<br><br>As far as I am aware, there is no such option and the code that implements<br>integer promotion is somewhat scattered across ³SemaExpr.cpp².<br><br>Also, I think your example code snippet contains a few ³i32²s too many. It<br>will be clearer to people what you are looking for if your code example is<br>consistent with your question.<br><br>Best,<br><br>Norman<br><br><br>>Message: 1<br>>Date: Fri, 27 May 2016 01:50:12 +0000<br>>From: Dilan Manatunga via cfe-dev <<a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a>><br>>To: <a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a><br>>Subject: [cfe-dev] Disable integer promotion<br>>Message-ID:<br>> <CAHpgGu4=<a href="mailto:jFC9ohQQZZMp2NMG3Hw0sE5U4-Lqrgb%2B6gcXv9SEtQ@mail.gmail.com" target="_blank">jFC9ohQQZZMp2NMG3Hw0sE5U4-Lqrgb+6gcXv9SEtQ@mail.gmail.com</a>><br>>Content-Type: text/plain; charset="utf-8"<br>><br>>Is there a way to disable integer promotion when performing math<br>>operations. For example, when compiling a statement such as this:<br>>int8_t a = 1;<br>>int8_t b = 2;<br>>int8_t c = a + b<br>><br>>The LLVM IR will be:<br>>%x = sext i32 %a to i32<br>>%y = sext i32 %b to i32<br>>%z = add nsw i32 %x, %y<br>>%c = trunc i32 %z to i16<br>><br>>Instead, it would simply compile to:<br>>$c = add nsw i32 %z, $y<br>><br>>-Dilan Manatunga<br>>-------------- next part --------------<br>>An HTML attachment was scrubbed...<br>>URL:<br>><<a href="http://lists.llvm.org/pipermail/cfe-dev/attachments/20160527/4a7920ab/att" target="_blank">http://lists.llvm.org/pipermail/cfe-dev/attachments/20160527/4a7920ab/att</a><br>>achment-0001.html><br>><br>>------------------------------<br><br><br>_______________________________________________<br>cfe-dev mailing list<br><a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev</a><o:p></o:p></span></p></blockquote></div></div></div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt'><span style='color:black'><br>_______________________________________________<br>cfe-dev mailing list<br><a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev</a><o:p></o:p></span></p></blockquote></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'> <o:p></o:p></span></p></div></div></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='color:black'>_______________________________________________<br>cfe-dev mailing list<br><a href="mailto:cfe-dev@lists.llvm.org" target="_blank">cfe-dev@lists.llvm.org</a><br><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-dev</a><o:p></o:p></span></p></blockquote></div></div></div></div></div></blockquote></div></div></body></html>