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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi İsmail,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I committed a patch (r221341) a few days ago to prevent the assembler and disassembler form accepting D16-D31 for the FPUs of Cortex-M cores, which only have 16 D registers. I’m assuming you were originally compiling for v7M? It looks like that file will need some additional conditionalization before it can be used for Cortex-M targets.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Oliver<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> cfe-dev-bounces@cs.uiuc.edu [mailto:cfe-dev-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Ismail Dönmez<br><b>Sent:</b> 07 November 2014 12:19<br><b>To:</b> Renato Golin<br><b>Cc:</b> cfe-dev@cs.uiuc.edu<br><b>Subject:</b> Re: [cfe-dev] ARM assembler regression?<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>On Fri, Nov 7, 2014 at 2:17 PM, Renato Golin <<a href="mailto:renato.golin@linaro.org" target="_blank">renato.golin@linaro.org</a>> wrote:<o:p></o:p></p><p class=MsoNormal style='margin-bottom:12.0pt'>On 6 November 2014 18:14, İsmail Dönmez <<a href="mailto:ismail@donmez.ws">ismail@donmez.ws</a>> wrote:<br>> Hmm indeed but this used to work fine? Any other sane options for mfpu?<br>> Especially for machines without a Neon unit (Marvell seems to have those).<br><br>You got me wrong. The fpu is sane, and that used to work, but it's not<br>a regression in the assembler, rather, in the assembly code. :)<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Yeah I found that later on and switch to -mfpu=vfpv3 as a temporary hack :)<o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm'><p class=MsoNormal>That code is assuming all VFP have 32 double registers, when that's<br>not true. I'll fix it.<o:p></o:p></p></blockquote><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Thanks!<o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div></div></div></div></div></div></body></html>