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<!-- BUGDESC Branch condition evaluates to a garbage value -->
<!-- BUGTYPE Branch condition evaluates to a garbage value -->
<!-- BUGCATEGORY Logic error -->
<!-- BUGFILE d:/build_dxl/build\DXL\Intercom\src\init\fpga.c -->
<!-- BUGLINE 119 -->
<!-- BUGPATHLENGTH 2 -->
<!-- BUGMETAEND -->
<!-- REPORTHEADER -->
<h3>Bug Summary</h3>
<table class="simpletable">
<tr><td class="rowname">File:</td><td>d:/build_dxl/build\DXL\Intercom\src\init\fpga.c</td></tr>
<tr><td class="rowname">Location:</td><td><a href="#EndPath">line 119, column 13</a></td></tr>
<tr><td class="rowname">Description:</td><td>Branch condition evaluates to a garbage value</td></tr>
</table>
<!-- REPORTSUMMARYEXTRA -->
<h3>Annotated Source Code</h3>
<table class="code">
<tr><td class="num" id="LN1">1</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN2">2</td><td class="line"> <span class='comment'>* SH4 Interface - FPGA interface (PCI).</span>
</td></tr>
<tr><td class="num" id="LN3">3</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN4">4</td><td class="line"> <span class='comment'>* FILENAME: FPGA.C</span>
</td></tr>
<tr><td class="num" id="LN5">5</td><td class="line"> <span class='comment'>* AUTHOR: Lloyd Elwood - Harding Instruments</span>
</td></tr>
<tr><td class="num" id="LN6">6</td><td class="line"> <span class='comment'>* CREATED: 2004-01-08</span>
</td></tr>
<tr><td class="num" id="LN7">7</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN8">8</td><td class="line"> <span class='comment'>* $Revision: 5 $</span>
</td></tr>
<tr><td class="num" id="LN9">9</td><td class="line"> <span class='comment'>* $Author: Lloyde $</span>
</td></tr>
<tr><td class="num" id="LN10">10</td><td class="line"> <span class='comment'>* $Date: 3-28-13 11:13a $</span>
</td></tr>
<tr><td class="num" id="LN11">11</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN12">12</td><td class="line"> <span class='comment'>****************************************************************************</span>
</td></tr>
<tr><td class="num" id="LN13">13</td><td class="line"> <span class='comment'>* Copyright (c) 2001-2003 Harding Instruments Co. Ltd. *</span>
</td></tr>
<tr><td class="num" id="LN14">14</td><td class="line"> <span class='comment'>* This document contains information which is proprietary and / or *</span>
</td></tr>
<tr><td class="num" id="LN15">15</td><td class="line"> <span class='comment'>* confidential to Harding Instrument Co. Ltd. Do not copy, disclose *</span>
</td></tr>
<tr><td class="num" id="LN16">16</td><td class="line"> <span class='comment'>* or use this document or its contents without written authorisation. *</span>
</td></tr>
<tr><td class="num" id="LN17">17</td><td class="line"> <span class='comment'>****************************************************************************</span>
</td></tr>
<tr><td class="num" id="LN18">18</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN19">19</td><td class="line"> <span class='comment'>* This contains the definitions used for the FPGA.</span>
</td></tr>
<tr><td class="num" id="LN20">20</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN21">21</td><td class="line"> <span class='comment'>* THIS FILE IS SHARED WITH BOOT LOADER CODE.</span>
</td></tr>
<tr><td class="num" id="LN22">22</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN23">23</td><td class="line">
</td></tr>
<tr><td class="num" id="LN24">24</td><td class="line"><span class='comment'>/* Include the memset command (only needed for solution engine compile). */</span>
</td></tr>
<tr><td class="num" id="LN25">25</td><td class="line"><span class='directive'>#include <string.h></span>
</td></tr>
<tr><td class="num" id="LN26">26</td><td class="line">
</td></tr>
<tr><td class="num" id="LN27">27</td><td class="line"><span class='comment'>/* Include standard DXL definitions and types. */</span>
</td></tr>
<tr><td class="num" id="LN28">28</td><td class="line"><span class='directive'>#include "general.h"</span>
</td></tr>
<tr><td class="num" id="LN29">29</td><td class="line">
</td></tr>
<tr><td class="num" id="LN30">30</td><td class="line"><span class='comment'>/* Include Nucleus and standard definitions. */</span>
</td></tr>
<tr><td class="num" id="LN31">31</td><td class="line"><span class='directive'>#include "fpga.h"</span>
</td></tr>
<tr><td class="num" id="LN32">32</td><td class="line">
</td></tr>
<tr><td class="num" id="LN33">33</td><td class="line"> <span class='comment'>/* Include the PCI access functions and addresses. */</span>
</td></tr>
<tr><td class="num" id="LN34">34</td><td class="line"><span class='directive'>#include "sys/pci.h"</span>
</td></tr>
<tr><td class="num" id="LN35">35</td><td class="line">
</td></tr>
<tr><td class="num" id="LN36">36</td><td class="line"><span class='comment'>/* These are only used for application code, not boot code. */</span>
</td></tr>
<tr><td class="num" id="LN37">37</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN38">38</td><td class="line">
</td></tr>
<tr><td class="num" id="LN39">39</td><td class="line"> <span class='comment'>/* This needs to access the global nvram for the FPGA control register. */</span>
</td></tr>
<tr><td class="num" id="LN40">40</td><td class="line"> <span class='directive'>#include "globalnv.h"</span>
</td></tr>
<tr><td class="num" id="LN41">41</td><td class="line">
</td></tr>
<tr><td class="num" id="LN42">42</td><td class="line"> <span class='comment'>/* Allocate a semaphore for the FPGA (currently not used). */</span>
</td></tr>
<tr><td class="num" id="LN43">43</td><td class="line"> NU_SEMAPHORE FPGA_sem;
</td></tr>
<tr><td class="num" id="LN44">44</td><td class="line">
</td></tr>
<tr><td class="num" id="LN45">45</td><td class="line"> <span class='comment'>/* Allocate a semaphore for the BATTLOAD Control lines */</span>
</td></tr>
<tr><td class="num" id="LN46">46</td><td class="line"> NU_SEMAPHORE FPGA_batt_sem;
</td></tr>
<tr><td class="num" id="LN47">47</td><td class="line"> INT32 FPGA_battload_count;
</td></tr>
<tr><td class="num" id="LN48">48</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN49">49</td><td class="line">
</td></tr>
<tr><td class="num" id="LN50">50</td><td class="line">
</td></tr>
<tr><td class="num" id="LN51">51</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN52">52</td><td class="line"> <span class='comment'>* All the variables in this file are really static but have been not declared</span>
</td></tr>
<tr><td class="num" id="LN53">53</td><td class="line"> <span class='comment'>* as such so that we can look at them using the debugger anytime we want.</span>
</td></tr>
<tr><td class="num" id="LN54">54</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN55">55</td><td class="line">
</td></tr>
<tr><td class="num" id="LN56">56</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN57">57</td><td class="line"> <span class='comment'>* Used to store the most loops required to read the FPGA. This is a debugging</span>
</td></tr>
<tr><td class="num" id="LN58">58</td><td class="line"> <span class='comment'>* thing that will probably need to be removed for speed purposes at some</span>
</td></tr>
<tr><td class="num" id="LN59">59</td><td class="line"> <span class='comment'>* point in time.</span>
</td></tr>
<tr><td class="num" id="LN60">60</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN61">61</td><td class="line"><span class='directive'>#if DXL_DEBUG_ENABLE</span>
</td></tr>
<tr><td class="num" id="LN62">62</td><td class="line"> UNSIGNED FPGA_longest;
</td></tr>
<tr><td class="num" id="LN63">63</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN64">64</td><td class="line">
</td></tr>
<tr><td class="num" id="LN65">65</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN66">66</td><td class="line"> <span class='comment'>* This is the last value written to the FPGA control register. This is</span>
</td></tr>
<tr><td class="num" id="LN67">67</td><td class="line"> <span class='comment'>* formatted as type fpga_control_t however it is defined as UINT32 to allow</span>
</td></tr>
<tr><td class="num" id="LN68">68</td><td class="line"> <span class='comment'>* us to perform logical AND/OR functions upon it (without continuously</span>
</td></tr>
<tr><td class="num" id="LN69">69</td><td class="line"> <span class='comment'>* casting it). When we write some fields in the corresponding I/O register</span>
</td></tr>
<tr><td class="num" id="LN70">70</td><td class="line"> <span class='comment'>* we update this so that we can perform the next write with the current</span>
</td></tr>
<tr><td class="num" id="LN71">71</td><td class="line"> <span class='comment'>* value of all the fields that we are not updating.</span>
</td></tr>
<tr><td class="num" id="LN72">72</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN73">73</td><td class="line">UINT32 FPGA_ctrl;
</td></tr>
<tr><td class="num" id="LN74">74</td><td class="line">
</td></tr>
<tr><td class="num" id="LN75">75</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN76">76</td><td class="line"> <span class='comment'>* Constants used to write the FPGA's lock/unlock bit. These assume that</span>
</td></tr>
<tr><td class="num" id="LN77">77</td><td class="line"> <span class='comment'>* the system initializes them to 0 upon startup.</span>
</td></tr>
<tr><td class="num" id="LN78">78</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN79">79</td><td class="line">fpga_control_t FPGA_unlock_bitmap;
</td></tr>
<tr><td class="num" id="LN80">80</td><td class="line">fpga_control_t FPGA_lock_bitmap;
</td></tr>
<tr><td class="num" id="LN81">81</td><td class="line">fpga_control_t FPGA_mask_bitmap;
</td></tr>
<tr><td class="num" id="LN82">82</td><td class="line">
</td></tr>
<tr><td class="num" id="LN83">83</td><td class="line"><span class='comment'>/* CEPT MUX's current settings. */</span>
</td></tr>
<tr><td class="num" id="LN84">84</td><td class="line">fpga_cept_mux_t FPGA_mux;
</td></tr>
<tr><td class="num" id="LN85">85</td><td class="line">
</td></tr>
<tr><td class="num" id="LN86">86</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN87">87</td><td class="line"> <span class='comment'>* Fpga_Xbus_Busy_Wait</span>
</td></tr>
<tr><td class="num" id="LN88">88</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN89">89</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN90">90</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN91">91</td><td class="line"> <span class='comment'>* Does a busy wait for the XBUS to become available.</span>
</td></tr>
<tr><td class="num" id="LN92">92</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN93">93</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN94">94</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN95">95</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN96">96</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN97">97</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN98">98</td><td class="line"> <span class='comment'>* Polls the XBUS to determine when it is available.</span>
</td></tr>
<tr><td class="num" id="LN99">99</td><td class="line"> <span class='comment'>* Declare the XBUS busy wait as an inline function.</span>
</td></tr>
<tr><td class="num" id="LN100">100</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN101">101</td><td class="line"><span class='directive'>#pragma inline(Fpga_Xbus_Busy_Wait)</span>
</td></tr>
<tr><td class="num" id="LN102">102</td><td class="line"><span class='keyword'>static</span> <span class='keyword'>void</span> Fpga_Xbus_Busy_Wait(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN103">103</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN104">104</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN105">105</td><td class="line"> <span class='comment'>/* Stores result of the XBUS busy request. */</span>
</td></tr>
<tr><td class="num" id="LN106">106</td><td class="line"> UINT32 rsp;
</td></tr>
<tr><td class="num" id="LN107">107</td><td class="line">
</td></tr>
<tr><td class="num" id="LN108">108</td><td class="line"><span class='directive'>#if DXL_DEBUG_ENABLE</span>
</td></tr>
<tr><td class="num" id="LN109">109</td><td class="line"> <span class='comment'>/* Initialize the number of loops to 0. */</span>
</td></tr>
<tr><td class="num" id="LN110">110</td><td class="line"> UNSIGNED fpga_samples = 0;
</td></tr>
<tr><td class="num" id="LN111">111</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN112">112</td><td class="line">
</td></tr>
<tr><td class="num" id="LN113">113</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN114">114</td><td class="line"> <span class='keyword'>do</span> {
</td></tr>
<tr><td class="num" id="LN115">115</td><td class="line"> rsp = PCI_Rd_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_STATUS_READ<span class='expansion'>0x0400</span></span>, 0);
</td></tr>
<tr><td class="num" id="LN116">116</td><td class="line"><span class='directive'>#if DXL_DEBUG_ENABLE</span>
</td></tr>
<tr><td class="num" id="LN117">117</td><td class="line"> fpga_samples++;
</td></tr>
<tr><td class="num" id="LN118">118</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN119">119</td><td class="line"> } <span class='keyword'>while</span>(<span class="mrange">((fpga_status_t *) &rsp)->xbus_busy</span>);
</td></tr>
<tr><td class="num"></td><td class="line"><div id="EndPath" class="msg msgEvent" style="margin-left:13ex"><table class="msgT"><tr><td valign="top"><div class="PathIndex PathIndexEvent">2</div></td><td><div class="PathNav"><a href="#Path1" title="Previous event (1)">←</a></div></td></td><td>Branch condition evaluates to a garbage value</td></tr></table></div></td></tr>
<tr><td class="num" id="LN120">120</td><td class="line">
</td></tr>
<tr><td class="num" id="LN121">121</td><td class="line"><span class='directive'>#if DXL_DEBUG_ENABLE</span>
</td></tr>
<tr><td class="num" id="LN122">122</td><td class="line"> <span class='comment'>/* Determine if the longest FPGA XBUS wait has been exceeded. */</span>
</td></tr>
<tr><td class="num" id="LN123">123</td><td class="line"> <span class='keyword'>if</span>(FPGA_longest < fpga_samples)
</td></tr>
<tr><td class="num" id="LN124">124</td><td class="line"> FPGA_longest = fpga_samples;
</td></tr>
<tr><td class="num" id="LN125">125</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN126">126</td><td class="line">
</td></tr>
<tr><td class="num" id="LN127">127</td><td class="line"><span class='directive'>#endif // ifndef SOLUTION ENGINE.</span>
</td></tr>
<tr><td class="num" id="LN128">128</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN129">129</td><td class="line">
</td></tr>
<tr><td class="num" id="LN130">130</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN131">131</td><td class="line"> <span class='comment'>* FPGA_Loopback_Write</span>
</td></tr>
<tr><td class="num" id="LN132">132</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN133">133</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN134">134</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN135">135</td><td class="line"> <span class='comment'>* Write the FPGA loopback register.</span>
</td></tr>
<tr><td class="num" id="LN136">136</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN137">137</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN138">138</td><td class="line"> <span class='comment'>* UINT32 data - The data to write to the FPGA loopback register.</span>
</td></tr>
<tr><td class="num" id="LN139">139</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN140">140</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN141">141</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN142">142</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN143">143</td><td class="line"> <span class='comment'>* This does not have to be called from a task in supervisory mode. However,</span>
</td></tr>
<tr><td class="num" id="LN144">144</td><td class="line"> <span class='comment'>* it does no harm if it is.</span>
</td></tr>
<tr><td class="num" id="LN145">145</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN146">146</td><td class="line"><span class='keyword'>void</span> FPGA_Loopback_Write(UINT32 data)
</td></tr>
<tr><td class="num" id="LN147">147</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN148">148</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN149">149</td><td class="line"> <span class='comment'>/* Put the SH4 in supervisory mode to allow PCI to access memory. */</span>
</td></tr>
<tr><td class="num" id="LN150">150</td><td class="line"> <span class='macro'>NU_SUPERV_USER_VARIABLES<span class='expansion'>TC_TCB *__sud_thread_ptr = (TC_TCB*)(TCD_Current_Thread);</span></span>
</td></tr>
<tr><td class="num" id="LN151">151</td><td class="line"> <span class='macro'>NU_SUPERVISOR_MODE()<span class='expansion'>SUC_Supervisor_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN152">152</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN153">153</td><td class="line">
</td></tr>
<tr><td class="num" id="LN154">154</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN155">155</td><td class="line"> <span class='comment'>/* Now we can write the loopback register. */</span>
</td></tr>
<tr><td class="num" id="LN156">156</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_LOOPBACK_READ<span class='expansion'>0x0000</span></span>, data, 0);
</td></tr>
<tr><td class="num" id="LN157">157</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN158">158</td><td class="line">
</td></tr>
<tr><td class="num" id="LN159">159</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN160">160</td><td class="line"> <span class='comment'>/* Remember to return to user mode. */</span>
</td></tr>
<tr><td class="num" id="LN161">161</td><td class="line"> <span class='macro'>NU_USER_MODE()<span class='expansion'>SUC_User_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN162">162</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN163">163</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN164">164</td><td class="line">
</td></tr>
<tr><td class="num" id="LN165">165</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN166">166</td><td class="line"> <span class='comment'>* FPGA_Loopback_Read</span>
</td></tr>
<tr><td class="num" id="LN167">167</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN168">168</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN169">169</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN170">170</td><td class="line"> <span class='comment'>* Write the FPGA loopback register.</span>
</td></tr>
<tr><td class="num" id="LN171">171</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN172">172</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN173">173</td><td class="line"> <span class='comment'>* UINT32 data - The data to write to the FPGA loopback register.</span>
</td></tr>
<tr><td class="num" id="LN174">174</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN175">175</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN176">176</td><td class="line"> <span class='comment'>* Returns data read from the loopback register. This will be the inverse</span>
</td></tr>
<tr><td class="num" id="LN177">177</td><td class="line"> <span class='comment'>* (if the loopback is working) of the value written to the loopback</span>
</td></tr>
<tr><td class="num" id="LN178">178</td><td class="line"> <span class='comment'>* register (see above).</span>
</td></tr>
<tr><td class="num" id="LN179">179</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN180">180</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN181">181</td><td class="line"> <span class='comment'>* This does not have to be called from a task in supervisory mode. However,</span>
</td></tr>
<tr><td class="num" id="LN182">182</td><td class="line"> <span class='comment'>* it does no harm if it is.</span>
</td></tr>
<tr><td class="num" id="LN183">183</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN184">184</td><td class="line">UINT32 FPGA_Loopback_Read(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN185">185</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN186">186</td><td class="line"> UINT32 read;
</td></tr>
<tr><td class="num" id="LN187">187</td><td class="line">
</td></tr>
<tr><td class="num" id="LN188">188</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN189">189</td><td class="line"> <span class='comment'>/* Put the SH4 in supervisory mode to allow PCI to access memory. */</span>
</td></tr>
<tr><td class="num" id="LN190">190</td><td class="line"> <span class='macro'>NU_SUPERV_USER_VARIABLES<span class='expansion'>TC_TCB *__sud_thread_ptr = (TC_TCB*)(TCD_Current_Thread);</span></span>
</td></tr>
<tr><td class="num" id="LN191">191</td><td class="line"> <span class='macro'>NU_SUPERVISOR_MODE()<span class='expansion'>SUC_Supervisor_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN192">192</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN193">193</td><td class="line">
</td></tr>
<tr><td class="num" id="LN194">194</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN195">195</td><td class="line"> read = PCI_Rd_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_LOOPBACK_READ<span class='expansion'>0x0000</span></span>, 0);
</td></tr>
<tr><td class="num" id="LN196">196</td><td class="line"><span class='directive'>#else</span>
</td></tr>
<tr><td class="num" id="LN197">197</td><td class="line"> read = 0;
</td></tr>
<tr><td class="num" id="LN198">198</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN199">199</td><td class="line">
</td></tr>
<tr><td class="num" id="LN200">200</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN201">201</td><td class="line"> <span class='comment'>/* Remember to return to user mode. */</span>
</td></tr>
<tr><td class="num" id="LN202">202</td><td class="line"> <span class='macro'>NU_USER_MODE()<span class='expansion'>SUC_User_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN203">203</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN204">204</td><td class="line">
</td></tr>
<tr><td class="num" id="LN205">205</td><td class="line"> <span class='comment'>/* Return the value read from the loopback register. */</span>
</td></tr>
<tr><td class="num" id="LN206">206</td><td class="line"> <span class='keyword'>return</span> read;
</td></tr>
<tr><td class="num" id="LN207">207</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN208">208</td><td class="line">
</td></tr>
<tr><td class="num" id="LN209">209</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN210">210</td><td class="line"> <span class='comment'>* FPGA_Control_Write</span>
</td></tr>
<tr><td class="num" id="LN211">211</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN212">212</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN213">213</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN214">214</td><td class="line"> <span class='comment'>* Writes the FPGA's control register.</span>
</td></tr>
<tr><td class="num" id="LN215">215</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN216">216</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN217">217</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN218">218</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN219">219</td><td class="line"> <span class='comment'>* fpga_control_t data - The data to write to the control register. This</span>
</td></tr>
<tr><td class="num" id="LN220">220</td><td class="line"> <span class='comment'>* will contain the copy of the control register to write to the FPGA.</span>
</td></tr>
<tr><td class="num" id="LN221">221</td><td class="line"> <span class='comment'>* The mask (see below) controls which of the bytes in this register are</span>
</td></tr>
<tr><td class="num" id="LN222">222</td><td class="line"> <span class='comment'>* really updated.</span>
</td></tr>
<tr><td class="num" id="LN223">223</td><td class="line"> <span class='comment'>* fpga_control_t mask - This is a bitmask of the bits which are going to</span>
</td></tr>
<tr><td class="num" id="LN224">224</td><td class="line"> <span class='comment'>* be changed in the FPGA control register. All the fields that we want</span>
</td></tr>
<tr><td class="num" id="LN225">225</td><td class="line"> <span class='comment'>* to change will be set to 1 and these will be replaced by the</span>
</td></tr>
<tr><td class="num" id="LN226">226</td><td class="line"> <span class='comment'>* corresponding values in the data parameter's corresponding fields.</span>
</td></tr>
<tr><td class="num" id="LN227">227</td><td class="line"> <span class='comment'>* Therefore, we take the current FPGA_cntl global, remove all bits in</span>
</td></tr>
<tr><td class="num" id="LN228">228</td><td class="line"> <span class='comment'>* it that are not 1 in the mask and then OR in the data bits.</span>
</td></tr>
<tr><td class="num" id="LN229">229</td><td class="line"> <span class='comment'>* global FPGA_cntl - This is the current FPGA_cntl that is being output</span>
</td></tr>
<tr><td class="num" id="LN230">230</td><td class="line"> <span class='comment'>* to the FPGA (i.e., the last value written). We have to keep this as</span>
</td></tr>
<tr><td class="num" id="LN231">231</td><td class="line"> <span class='comment'>* a global because different calls to this function will only be</span>
</td></tr>
<tr><td class="num" id="LN232">232</td><td class="line"> <span class='comment'>* updating certain bits (as per the mask). Therefore, we have to ensure</span>
</td></tr>
<tr><td class="num" id="LN233">233</td><td class="line"> <span class='comment'>* that all the other bits will be left alone. This requires that we</span>
</td></tr>
<tr><td class="num" id="LN234">234</td><td class="line"> <span class='comment'>* use this global variable.</span>
</td></tr>
<tr><td class="num" id="LN235">235</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN236">236</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN237">237</td><td class="line"> <span class='comment'>* This locks the task (so it runs to completion) as this is critical code.</span>
</td></tr>
<tr><td class="num" id="LN238">238</td><td class="line"> <span class='comment'>* This puts the task in supervisor mode and exits supervisor mode after</span>
</td></tr>
<tr><td class="num" id="LN239">239</td><td class="line"> <span class='comment'>* it exits so that the calling task does not have to be in supervisor</span>
</td></tr>
<tr><td class="num" id="LN240">240</td><td class="line"> <span class='comment'>* mode when this is called. Note, however, that the each task keeps its</span>
</td></tr>
<tr><td class="num" id="LN241">241</td><td class="line"> <span class='comment'>* copy of the supervisor mode flag and how nested levels of supervisor</span>
</td></tr>
<tr><td class="num" id="LN242">242</td><td class="line"> <span class='comment'>* mode functions have been called. Therefore, if the caller is in</span>
</td></tr>
<tr><td class="num" id="LN243">243</td><td class="line"> <span class='comment'>* supervisor mode this function will not return to user mode when it ends.</span>
</td></tr>
<tr><td class="num" id="LN244">244</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN245">245</td><td class="line"><span class='keyword'>void</span> FPGA_Control_Write(fpga_control_t data, fpga_control_t mask)
</td></tr>
<tr><td class="num" id="LN246">246</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN247">247</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN248">248</td><td class="line"> <span class='comment'>/* Put the SH4 in supervisory mode to allow PCI to access memory. */</span>
</td></tr>
<tr><td class="num" id="LN249">249</td><td class="line"> <span class='macro'>NU_SUPERV_USER_VARIABLES<span class='expansion'>TC_TCB *__sud_thread_ptr = (TC_TCB*)(TCD_Current_Thread);</span></span>
</td></tr>
<tr><td class="num" id="LN250">250</td><td class="line"> <span class='macro'>NU_SUPERVISOR_MODE()<span class='expansion'>SUC_Supervisor_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN251">251</td><td class="line">
</td></tr>
<tr><td class="num" id="LN252">252</td><td class="line"> {
</td></tr>
<tr><td class="num" id="LN253">253</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN254">254</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN255">255</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN256">256</td><td class="line">
</td></tr>
<tr><td class="num" id="LN257">257</td><td class="line"> <span class='comment'>/* Used to store the XBUS busy status (must be idle). */</span>
</td></tr>
<tr><td class="num" id="LN258">258</td><td class="line"> UINT32 rsp;
</td></tr>
<tr><td class="num" id="LN259">259</td><td class="line">
</td></tr>
<tr><td class="num" id="LN260">260</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN261">261</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN262">262</td><td class="line">
</td></tr>
<tr><td class="num" id="LN263">263</td><td class="line"> <span class='comment'>/* Update the global variable with the new settings. */</span>
</td></tr>
<tr><td class="num" id="LN264">264</td><td class="line"> FPGA_ctrl = (*(UINT32 *)&data) | (FPGA_ctrl & ~(*(UINT32 *)&mask));
</td></tr>
<tr><td class="num" id="LN265">265</td><td class="line">
</td></tr>
<tr><td class="num" id="LN266">266</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN267">267</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN268">268</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN269">269</td><td class="line">
</td></tr>
<tr><td class="num" id="LN270">270</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN271">271</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN272">272</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN273">273</td><td class="line"> }
</td></tr>
<tr><td class="num" id="LN274">274</td><td class="line">
</td></tr>
<tr><td class="num" id="LN275">275</td><td class="line"> <span class='comment'>/* Remember to return to user mode. */</span>
</td></tr>
<tr><td class="num" id="LN276">276</td><td class="line"> <span class='macro'>NU_USER_MODE()<span class='expansion'>SUC_User_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN277">277</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN278">278</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN279">279</td><td class="line">
</td></tr>
<tr><td class="num" id="LN280">280</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN281">281</td><td class="line"> <span class='comment'>* FPGA_Control_Write_No_Preempt</span>
</td></tr>
<tr><td class="num" id="LN282">282</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN283">283</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN284">284</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN285">285</td><td class="line"> <span class='comment'>* Writes the FPGA's control register assuming the caller has preemption</span>
</td></tr>
<tr><td class="num" id="LN286">286</td><td class="line"> <span class='comment'>* disabled.</span>
</td></tr>
<tr><td class="num" id="LN287">287</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN288">288</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN289">289</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN290">290</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN291">291</td><td class="line"> <span class='comment'>* fpga_control_t data - The data to write to the control register. This</span>
</td></tr>
<tr><td class="num" id="LN292">292</td><td class="line"> <span class='comment'>* will contain the copy of the control register to write to the FPGA.</span>
</td></tr>
<tr><td class="num" id="LN293">293</td><td class="line"> <span class='comment'>* The mask (see below) controls which of the bytes in this register are</span>
</td></tr>
<tr><td class="num" id="LN294">294</td><td class="line"> <span class='comment'>* really updated.</span>
</td></tr>
<tr><td class="num" id="LN295">295</td><td class="line"> <span class='comment'>* fpga_control_t mask - This is a bitmask of the bits which are going to</span>
</td></tr>
<tr><td class="num" id="LN296">296</td><td class="line"> <span class='comment'>* be changed in the FPGA control register. All the fields that we want</span>
</td></tr>
<tr><td class="num" id="LN297">297</td><td class="line"> <span class='comment'>* to change will be set to 1 and these will be replaced by the</span>
</td></tr>
<tr><td class="num" id="LN298">298</td><td class="line"> <span class='comment'>* corresponding values in the data parameter's corresponding fields.</span>
</td></tr>
<tr><td class="num" id="LN299">299</td><td class="line"> <span class='comment'>* Therefore, we take the current FPGA_cntl global, remove all bits in</span>
</td></tr>
<tr><td class="num" id="LN300">300</td><td class="line"> <span class='comment'>* it that are not 1 in the mask and then OR in the data bits.</span>
</td></tr>
<tr><td class="num" id="LN301">301</td><td class="line"> <span class='comment'>* global FPGA_cntl - This is the current FPGA_cntl that is being output</span>
</td></tr>
<tr><td class="num" id="LN302">302</td><td class="line"> <span class='comment'>* to the FPGA (i.e., the last value written). We have to keep this as</span>
</td></tr>
<tr><td class="num" id="LN303">303</td><td class="line"> <span class='comment'>* a global because different calls to this function will only be</span>
</td></tr>
<tr><td class="num" id="LN304">304</td><td class="line"> <span class='comment'>* updating certain bits (as per the mask). Therefore, we have to ensure</span>
</td></tr>
<tr><td class="num" id="LN305">305</td><td class="line"> <span class='comment'>* that all the other bits will be left alone. This requires that we</span>
</td></tr>
<tr><td class="num" id="LN306">306</td><td class="line"> <span class='comment'>* use this global variable.</span>
</td></tr>
<tr><td class="num" id="LN307">307</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN308">308</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN309">309</td><td class="line"> <span class='comment'>* This must be called with preemption turned off!</span>
</td></tr>
<tr><td class="num" id="LN310">310</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN311">311</td><td class="line"><span class='keyword'>void</span> FPGA_Control_Write_No_Preempt(fpga_control_t data, fpga_control_t mask)
</td></tr>
<tr><td class="num" id="LN312">312</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN313">313</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN314">314</td><td class="line"> <span class='comment'>/* Put the SH4 in supervisory mode to allow PCI to access memory. */</span>
</td></tr>
<tr><td class="num" id="LN315">315</td><td class="line"> <span class='macro'>NU_SUPERV_USER_VARIABLES<span class='expansion'>TC_TCB *__sud_thread_ptr = (TC_TCB*)(TCD_Current_Thread);</span></span>
</td></tr>
<tr><td class="num" id="LN316">316</td><td class="line"> <span class='macro'>NU_SUPERVISOR_MODE()<span class='expansion'>SUC_Supervisor_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN317">317</td><td class="line">
</td></tr>
<tr><td class="num" id="LN318">318</td><td class="line"> {
</td></tr>
<tr><td class="num" id="LN319">319</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN320">320</td><td class="line"> <span class='comment'>/* Used to store the XBUS busy status (must be idle). */</span>
</td></tr>
<tr><td class="num" id="LN321">321</td><td class="line"> UINT32 rsp;
</td></tr>
<tr><td class="num" id="LN322">322</td><td class="line">
</td></tr>
<tr><td class="num" id="LN323">323</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN324">324</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN325">325</td><td class="line">
</td></tr>
<tr><td class="num" id="LN326">326</td><td class="line"> <span class='comment'>/* Update the global variable with the new settings. */</span>
</td></tr>
<tr><td class="num" id="LN327">327</td><td class="line"> FPGA_ctrl = (*(UINT32 *)&data) | (FPGA_ctrl & ~(*(UINT32 *)&mask));
</td></tr>
<tr><td class="num" id="LN328">328</td><td class="line">
</td></tr>
<tr><td class="num" id="LN329">329</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN330">330</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN331">331</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN332">332</td><td class="line">
</td></tr>
<tr><td class="num" id="LN333">333</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN334">334</td><td class="line"> }
</td></tr>
<tr><td class="num" id="LN335">335</td><td class="line">
</td></tr>
<tr><td class="num" id="LN336">336</td><td class="line"> <span class='comment'>/* Remember to return to user mode. */</span>
</td></tr>
<tr><td class="num" id="LN337">337</td><td class="line"> <span class='macro'>NU_USER_MODE()<span class='expansion'>SUC_User_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN338">338</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN339">339</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN340">340</td><td class="line">
</td></tr>
<tr><td class="num" id="LN341">341</td><td class="line">
</td></tr>
<tr><td class="num" id="LN342">342</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN343">343</td><td class="line"> <span class='comment'>* FPGA_Batt_Load</span>
</td></tr>
<tr><td class="num" id="LN344">344</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN345">345</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN346">346</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN347">347</td><td class="line"> <span class='comment'>* Writes to the FPGA battery load enable/disable line to control if the</span>
</td></tr>
<tr><td class="num" id="LN348">348</td><td class="line"> <span class='comment'>* battery load is connected or disconnected</span>
</td></tr>
<tr><td class="num" id="LN349">349</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN350">350</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN351">351</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN352">352</td><td class="line"> <span class='comment'>* Calls the FPGA_Control_Write() command to perform the operation.</span>
</td></tr>
<tr><td class="num" id="LN353">353</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN354">354</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN355">355</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN356">356</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN357">357</td><td class="line"><span class='keyword'>void</span> FPGA_Batt_Load(<span class='keyword'>int</span> load_enable)
</td></tr>
<tr><td class="num" id="LN358">358</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN359">359</td><td class="line"> <span class='comment'>/* Control for the battery enable/disable. */</span>
</td></tr>
<tr><td class="num" id="LN360">360</td><td class="line"> fpga_control_t data, mask;
</td></tr>
<tr><td class="num" id="LN361">361</td><td class="line"> STATUS status;
</td></tr>
<tr><td class="num" id="LN362">362</td><td class="line">
</td></tr>
<tr><td class="num" id="LN363">363</td><td class="line"> <span class='comment'>/* We will only ever set the vbatt_en bit so set its mask now. */</span>
</td></tr>
<tr><td class="num" id="LN364">364</td><td class="line"> memset(&mask, 0, <span class='keyword'>sizeof</span>(mask));
</td></tr>
<tr><td class="num" id="LN365">365</td><td class="line"> mask.vbatt_en = -1;
</td></tr>
<tr><td class="num" id="LN366">366</td><td class="line">
</td></tr>
<tr><td class="num" id="LN367">367</td><td class="line"> <span class='comment'>/* Clear the data structure prior to calling FPGA_Control_Write. */</span>
</td></tr>
<tr><td class="num" id="LN368">368</td><td class="line"> memset(&data, 0, <span class='keyword'>sizeof</span>(data));
</td></tr>
<tr><td class="num" id="LN369">369</td><td class="line">
</td></tr>
<tr><td class="num" id="LN370">370</td><td class="line"> <span class='comment'>/* If the load is enabled, clear the data bit, otherwise set. */</span>
</td></tr>
<tr><td class="num" id="LN371">371</td><td class="line"> data.vbatt_en = load_enable ? 0 : 1; <span class='comment'>/* Active low load enabled */</span>
</td></tr>
<tr><td class="num" id="LN372">372</td><td class="line">
</td></tr>
<tr><td class="num" id="LN373">373</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN374">374</td><td class="line"> <span class='keyword'>if</span> (load_enable)
</td></tr>
<tr><td class="num" id="LN375">375</td><td class="line"> { <span class='comment'>/* Grab the battload semaphore */</span>
</td></tr>
<tr><td class="num" id="LN376">376</td><td class="line"> <span class='macro'>NU_Obtain_Semaphore<span class='expansion'>SMCE_Obtain_Semaphore</span></span>(&FPGA_batt_sem, <span class='macro'>NU_SUSPEND<span class='expansion'>0xFFFFFFFFUL</span></span>);
</td></tr>
<tr><td class="num" id="LN377">377</td><td class="line">
</td></tr>
<tr><td class="num" id="LN378">378</td><td class="line"> <span class='comment'>/* Increment the load enable count */</span>
</td></tr>
<tr><td class="num" id="LN379">379</td><td class="line"> FPGA_battload_count++;
</td></tr>
<tr><td class="num" id="LN380">380</td><td class="line">
</td></tr>
<tr><td class="num" id="LN381">381</td><td class="line"> <span class='comment'>/* Perform the actual FPGA control write to the batt select line */</span>
</td></tr>
<tr><td class="num" id="LN382">382</td><td class="line"> FPGA_Control_Write(data, mask);
</td></tr>
<tr><td class="num" id="LN383">383</td><td class="line">
</td></tr>
<tr><td class="num" id="LN384">384</td><td class="line"> <span class='comment'>/* We are done. Release the semaphore */</span>
</td></tr>
<tr><td class="num" id="LN385">385</td><td class="line"> <span class='macro'>NU_Release_Semaphore<span class='expansion'>SMCE_Release_Semaphore</span></span>(&FPGA_batt_sem);
</td></tr>
<tr><td class="num" id="LN386">386</td><td class="line"> }
</td></tr>
<tr><td class="num" id="LN387">387</td><td class="line"> <span class='keyword'>else</span>
</td></tr>
<tr><td class="num" id="LN388">388</td><td class="line"> { <span class='comment'>/* We want to release the battery load. Grab the sem */</span>
</td></tr>
<tr><td class="num" id="LN389">389</td><td class="line"> <span class='macro'>NU_Obtain_Semaphore<span class='expansion'>SMCE_Obtain_Semaphore</span></span>(&FPGA_batt_sem, <span class='macro'>NU_SUSPEND<span class='expansion'>0xFFFFFFFFUL</span></span>);
</td></tr>
<tr><td class="num" id="LN390">390</td><td class="line">
</td></tr>
<tr><td class="num" id="LN391">391</td><td class="line"> <span class='comment'>/* Decrement the battery load count */</span>
</td></tr>
<tr><td class="num" id="LN392">392</td><td class="line"> FPGA_battload_count--;
</td></tr>
<tr><td class="num" id="LN393">393</td><td class="line">
</td></tr>
<tr><td class="num" id="LN394">394</td><td class="line"> <span class='comment'>/* If the load count is now zero, we can release the battery load */</span>
</td></tr>
<tr><td class="num" id="LN395">395</td><td class="line"> <span class='keyword'>if</span> (FPGA_battload_count == 0)
</td></tr>
<tr><td class="num" id="LN396">396</td><td class="line"> FPGA_Control_Write(data, mask);
</td></tr>
<tr><td class="num" id="LN397">397</td><td class="line">
</td></tr>
<tr><td class="num" id="LN398">398</td><td class="line"> <span class='comment'>/* Release the semaphore */</span>
</td></tr>
<tr><td class="num" id="LN399">399</td><td class="line"> <span class='macro'>NU_Release_Semaphore<span class='expansion'>SMCE_Release_Semaphore</span></span>(&FPGA_batt_sem);
</td></tr>
<tr><td class="num" id="LN400">400</td><td class="line"> }
</td></tr>
<tr><td class="num" id="LN401">401</td><td class="line"><span class='directive'>#else</span>
</td></tr>
<tr><td class="num" id="LN402">402</td><td class="line"> <span class='comment'>/* No nucleus. Just write out the control data */</span>
</td></tr>
<tr><td class="num" id="LN403">403</td><td class="line"> FPGA_Control_Write(data, mask);
</td></tr>
<tr><td class="num" id="LN404">404</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN405">405</td><td class="line">
</td></tr>
<tr><td class="num" id="LN406">406</td><td class="line"> <span class='keyword'>return</span>;
</td></tr>
<tr><td class="num" id="LN407">407</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN408">408</td><td class="line">
</td></tr>
<tr><td class="num" id="LN409">409</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN410">410</td><td class="line"> <span class='comment'>* FPGA_Configuration_Read</span>
</td></tr>
<tr><td class="num" id="LN411">411</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN412">412</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN413">413</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN414">414</td><td class="line"> <span class='comment'>* Reads the FPGA's CEPT/Keypad configuration (Only done on startup!)</span>
</td></tr>
<tr><td class="num" id="LN415">415</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN416">416</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN417">417</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN418">418</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN419">419</td><td class="line"> <span class='comment'>* Returns the configuration structure so we can determine CEPT and keypad</span>
</td></tr>
<tr><td class="num" id="LN420">420</td><td class="line"> <span class='comment'>* configuration. This structure is the same as the status structure but</span>
</td></tr>
<tr><td class="num" id="LN421">421</td><td class="line"> <span class='comment'>* was named differently because it used to be separate from status.</span>
</td></tr>
<tr><td class="num" id="LN422">422</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN423">423</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN424">424</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN425">425</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN426">426</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN427">427</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN428">428</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN429">429</td><td class="line"> <span class='comment'>* This must do a keypad request to read the keypad/cept bits.</span>
</td></tr>
<tr><td class="num" id="LN430">430</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN431">431</td><td class="line">fpga_configuration_t FPGA_Configuration_Read(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN432">432</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN433">433</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN434">434</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN435">435</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN436">436</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN437">437</td><td class="line">
</td></tr>
<tr><td class="num" id="LN438">438</td><td class="line"> <span class='comment'>/* Store the value read from the FPGA. */</span>
</td></tr>
<tr><td class="num" id="LN439">439</td><td class="line"> UINT32 read;
</td></tr>
<tr><td class="num" id="LN440">440</td><td class="line">
</td></tr>
<tr><td class="num" id="LN441">441</td><td class="line"> <span class='comment'>/* The request and response for the xbus. */</span>
</td></tr>
<tr><td class="num" id="LN442">442</td><td class="line"> UINT32 rsp, req = 0;
</td></tr>
<tr><td class="num" id="LN443">443</td><td class="line">
</td></tr>
<tr><td class="num" id="LN444">444</td><td class="line"> <span class='comment'>/* The bits to mask out and the bits to set (initialize to 0). */</span>
</td></tr>
<tr><td class="num" id="LN445">445</td><td class="line"> UINT32 set = 0, mask = 0;
</td></tr>
<tr><td class="num" id="LN446">446</td><td class="line">
</td></tr>
<tr><td class="num" id="LN447">447</td><td class="line"> <span class='comment'>/* Setup Xbus to read any keypad row in set and mask. */</span>
</td></tr>
<tr><td class="num" id="LN448">448</td><td class="line"> ((fpga_control_t *)&set)->req_keypad = 1;
</td></tr>
<tr><td class="num" id="LN449">449</td><td class="line"> ((fpga_control_t *)&mask)->req_keypad = -1;
</td></tr>
<tr><td class="num" id="LN450">450</td><td class="line"> ((fpga_control_t *)&set)->keyrow = 1;
</td></tr>
<tr><td class="num" id="LN451">451</td><td class="line"> ((fpga_control_t *)&mask)->keyrow = -1;
</td></tr>
<tr><td class="num" id="LN452">452</td><td class="line">
</td></tr>
<tr><td class="num" id="LN453">453</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN454">454</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN455">455</td><td class="line">
</td></tr>
<tr><td class="num" id="LN456">456</td><td class="line"> <span class='comment'>/* Update the global variable with the new settings. */</span>
</td></tr>
<tr><td class="num" id="LN457">457</td><td class="line"> FPGA_ctrl = set | (FPGA_ctrl & ~mask);
</td></tr>
<tr><td class="num" id="LN458">458</td><td class="line">
</td></tr>
<tr><td class="num" id="LN459">459</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN460">460</td><td class="line"> <span class='comment'>/* Now do the write to the control register. */</span>
</td></tr>
<tr><td class="num" id="LN461">461</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN462">462</td><td class="line">
</td></tr>
<tr><td class="num" id="LN463">463</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN464">464</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN465">465</td><td class="line">
</td></tr>
<tr><td class="num" id="LN466">466</td><td class="line"> <span class='comment'>/* Extra read when XBUS is not busy. */</span>
</td></tr>
<tr><td class="num" id="LN467">467</td><td class="line"> rsp = PCI_Rd_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_STATUS_READ<span class='expansion'>0x0400</span></span>, 0);
</td></tr>
<tr><td class="num" id="LN468">468</td><td class="line"><span class='directive'>#else</span>
</td></tr>
<tr><td class="num" id="LN469">469</td><td class="line"> <span class='comment'>/* No FPGA stuffed so act like there is no keypad/cept. */</span>
</td></tr>
<tr><td class="num" id="LN470">470</td><td class="line"> ((fpga_status_t *) &rsp)->cept_configuration = 3;
</td></tr>
<tr><td class="num" id="LN471">471</td><td class="line"> ((fpga_status_t *) &rsp)->keypad_configuration = 3;
</td></tr>
<tr><td class="num" id="LN472">472</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN473">473</td><td class="line">
</td></tr>
<tr><td class="num" id="LN474">474</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN475">475</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN476">476</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN477">477</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN478">478</td><td class="line">
</td></tr>
<tr><td class="num" id="LN479">479</td><td class="line"> <span class='comment'>/* Return the configuration read. */</span>
</td></tr>
<tr><td class="num" id="LN480">480</td><td class="line"> <span class='keyword'>return</span> * (fpga_status_t *)&rsp;
</td></tr>
<tr><td class="num" id="LN481">481</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN482">482</td><td class="line">
</td></tr>
<tr><td class="num" id="LN483">483</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN484">484</td><td class="line"> <span class='comment'>* FPGA_Status_Read</span>
</td></tr>
<tr><td class="num" id="LN485">485</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN486">486</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN487">487</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN488">488</td><td class="line"> <span class='comment'>* Read the FPGA's status register.</span>
</td></tr>
<tr><td class="num" id="LN489">489</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN490">490</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN491">491</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN492">492</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN493">493</td><td class="line"> <span class='comment'>* Returns the value read from the FPGA status register.</span>
</td></tr>
<tr><td class="num" id="LN494">494</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN495">495</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN496">496</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN497">497</td><td class="line"> <span class='comment'>* execution of this function. This function switches to supervisor mode</span>
</td></tr>
<tr><td class="num" id="LN498">498</td><td class="line"> <span class='comment'>* before it reads the PCI. However, the caller can be in supervisor mode</span>
</td></tr>
<tr><td class="num" id="LN499">499</td><td class="line"> <span class='comment'>* when this is called because the call to revert to user mode will only</span>
</td></tr>
<tr><td class="num" id="LN500">500</td><td class="line"> <span class='comment'>* do so if the caller was not already in supervisor mode.</span>
</td></tr>
<tr><td class="num" id="LN501">501</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN502">502</td><td class="line">fpga_status_t FPGA_Status_Read(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN503">503</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN504">504</td><td class="line"> <span class='comment'>/* Value read from the FPGA. */</span>
</td></tr>
<tr><td class="num" id="LN505">505</td><td class="line"> UINT32 read;
</td></tr>
<tr><td class="num" id="LN506">506</td><td class="line">
</td></tr>
<tr><td class="num" id="LN507">507</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN508">508</td><td class="line"> <span class='comment'>/* Put the SH4 in supervisory mode to allow PCI to access memory. */</span>
</td></tr>
<tr><td class="num" id="LN509">509</td><td class="line"> <span class='macro'>NU_SUPERV_USER_VARIABLES<span class='expansion'>TC_TCB *__sud_thread_ptr = (TC_TCB*)(TCD_Current_Thread);</span></span>
</td></tr>
<tr><td class="num" id="LN510">510</td><td class="line"> <span class='macro'>NU_SUPERVISOR_MODE()<span class='expansion'>SUC_Supervisor_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN511">511</td><td class="line">
</td></tr>
<tr><td class="num" id="LN512">512</td><td class="line"> {
</td></tr>
<tr><td class="num" id="LN513">513</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN514">514</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN515">515</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN516">516</td><td class="line">
</td></tr>
<tr><td class="num" id="LN517">517</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN518">518</td><td class="line"> <span class='comment'>/* Read the PCI status register. */</span>
</td></tr>
<tr><td class="num" id="LN519">519</td><td class="line"> read = PCI_Rd_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_STATUS_READ<span class='expansion'>0x0400</span></span>, 0);
</td></tr>
<tr><td class="num" id="LN520">520</td><td class="line"><span class='directive'>#else</span>
</td></tr>
<tr><td class="num" id="LN521">521</td><td class="line"> <span class='comment'>/* Fill in some useful defaults (i.e., no CEPT). */</span>
</td></tr>
<tr><td class="num" id="LN522">522</td><td class="line"> ((fpga_status_t *) &read)->version = 0xDEAF;
</td></tr>
<tr><td class="num" id="LN523">523</td><td class="line"> ((fpga_status_t *) &read)->two_hundred_mhz_dsp = 0;
</td></tr>
<tr><td class="num" id="LN524">524</td><td class="line"> ((fpga_status_t *) &read)->hwid = 0;
</td></tr>
<tr><td class="num" id="LN525">525</td><td class="line"> ((fpga_status_t *) &read)->xbus_busy = 0;
</td></tr>
<tr><td class="num" id="LN526">526</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN527">527</td><td class="line">
</td></tr>
<tr><td class="num" id="LN528">528</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN529">529</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN530">530</td><td class="line"> <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN531">531</td><td class="line"> }
</td></tr>
<tr><td class="num" id="LN532">532</td><td class="line">
</td></tr>
<tr><td class="num" id="LN533">533</td><td class="line"> <span class='comment'>/* Remember to return to user mode. */</span>
</td></tr>
<tr><td class="num" id="LN534">534</td><td class="line"> <span class='macro'>NU_USER_MODE()<span class='expansion'>SUC_User_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN535">535</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN536">536</td><td class="line">
</td></tr>
<tr><td class="num" id="LN537">537</td><td class="line"> <span class='comment'>/* Return the flags that we read. */</span>
</td></tr>
<tr><td class="num" id="LN538">538</td><td class="line"> <span class='keyword'>return</span> * (fpga_status_t *) &read;
</td></tr>
<tr><td class="num" id="LN539">539</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN540">540</td><td class="line">
</td></tr>
<tr><td class="num" id="LN541">541</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN542">542</td><td class="line"> <span class='comment'>* FPGA_Keypad_Setup</span>
</td></tr>
<tr><td class="num" id="LN543">543</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN544">544</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN545">545</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN546">546</td><td class="line"> <span class='comment'>* Setup the keypad so that we will be able to read the keypad's row (after</span>
</td></tr>
<tr><td class="num" id="LN547">547</td><td class="line"> <span class='comment'>* waiting for several milliseconds).</span>
</td></tr>
<tr><td class="num" id="LN548">548</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN549">549</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN550">550</td><td class="line"> <span class='comment'>* UINT8 row - The row of the keypad to read.</span>
</td></tr>
<tr><td class="num" id="LN551">551</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN552">552</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN553">553</td><td class="line"> <span class='comment'>* Returns the value read from the row in question.</span>
</td></tr>
<tr><td class="num" id="LN554">554</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN555">555</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN556">556</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN557">557</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN558">558</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN559">559</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN560">560</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN561">561</td><td class="line"><span class='keyword'>void</span> FPGA_Keypad_Setup(UINT8 row)
</td></tr>
<tr><td class="num" id="LN562">562</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN563">563</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN564">564</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN565">565</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN566">566</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN567">567</td><td class="line">
</td></tr>
<tr><td class="num" id="LN568">568</td><td class="line"> <span class='comment'>/* The bits to mask out and the bits to set (initialize to 0). */</span>
</td></tr>
<tr><td class="num" id="LN569">569</td><td class="line"> UINT32 set = 0, mask = 0;
</td></tr>
<tr><td class="num" id="LN570">570</td><td class="line">
</td></tr>
<tr><td class="num" id="LN571">571</td><td class="line"> <span class='comment'>/* The response status. */</span>
</td></tr>
<tr><td class="num" id="LN572">572</td><td class="line"> UINT32 rsp;
</td></tr>
<tr><td class="num" id="LN573">573</td><td class="line">
</td></tr>
<tr><td class="num" id="LN574">574</td><td class="line"> <span class='comment'>/* Setup Xbus to read keypad's row in set and mask. */</span>
</td></tr>
<tr><td class="num" id="LN575">575</td><td class="line"> ((fpga_control_t *)&set)->req_keypad = 0;
</td></tr>
<tr><td class="num" id="LN576">576</td><td class="line"> ((fpga_control_t *)&mask)->req_keypad = -1;
</td></tr>
<tr><td class="num" id="LN577">577</td><td class="line"> ((fpga_control_t *)&set)->keyrow = 1<<row;
</td></tr>
<tr><td class="num" id="LN578">578</td><td class="line"> ((fpga_control_t *)&mask)->keyrow = -1;
</td></tr>
<tr><td class="num" id="LN579">579</td><td class="line">
</td></tr>
<tr><td class="num" id="LN580">580</td><td class="line"> <span class='comment'>/* Update the global variable with the new settings. */</span>
</td></tr>
<tr><td class="num" id="LN581">581</td><td class="line"> FPGA_ctrl = set | (FPGA_ctrl & ~mask);
</td></tr>
<tr><td class="num" id="LN582">582</td><td class="line">
</td></tr>
<tr><td class="num" id="LN583">583</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN584">584</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN585">585</td><td class="line">
</td></tr>
<tr><td class="num" id="LN586">586</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN587">587</td><td class="line"> <span class='comment'>/* Now do the write to the control register. */</span>
</td></tr>
<tr><td class="num" id="LN588">588</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN589">589</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN590">590</td><td class="line">
</td></tr>
<tr><td class="num" id="LN591">591</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN592">592</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN593">593</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN594">594</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN595">595</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN596">596</td><td class="line">
</td></tr>
<tr><td class="num" id="LN597">597</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN598">598</td><td class="line"> <span class='comment'>* FPGA_Keypad_Read</span>
</td></tr>
<tr><td class="num" id="LN599">599</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN600">600</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN601">601</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN602">602</td><td class="line"> <span class='comment'>* Write to the Keypad controller. This will write the row that we will</span>
</td></tr>
<tr><td class="num" id="LN603">603</td><td class="line"> <span class='comment'>* be reading the next time that we access the keypad..</span>
</td></tr>
<tr><td class="num" id="LN604">604</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN605">605</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN606">606</td><td class="line"> <span class='comment'>* UINT8 row - The row that we were attempting to read.</span>
</td></tr>
<tr><td class="num" id="LN607">607</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN608">608</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN609">609</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN610">610</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN611">611</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN612">612</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN613">613</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN614">614</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN615">615</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN616">616</td><td class="line">UINT8 FPGA_Keypad_Read(UINT8 row)
</td></tr>
<tr><td class="num" id="LN617">617</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN618">618</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN619">619</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN620">620</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN621">621</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN622">622</td><td class="line">
</td></tr>
<tr><td class="num" id="LN623">623</td><td class="line"> <span class='comment'>/* The request and response for the xbus. */</span>
</td></tr>
<tr><td class="num" id="LN624">624</td><td class="line"> UINT32 rsp, req = 0;
</td></tr>
<tr><td class="num" id="LN625">625</td><td class="line">
</td></tr>
<tr><td class="num" id="LN626">626</td><td class="line"> <span class='comment'>/* The bits to mask out and the bits to set (initialize to 0). */</span>
</td></tr>
<tr><td class="num" id="LN627">627</td><td class="line"> UINT32 set = 0, mask = 0;
</td></tr>
<tr><td class="num" id="LN628">628</td><td class="line">
</td></tr>
<tr><td class="num" id="LN629">629</td><td class="line"> <span class='comment'>/* Setup Xbus to read keypad's row in set and mask. */</span>
</td></tr>
<tr><td class="num" id="LN630">630</td><td class="line"> ((fpga_control_t *)&set)->req_keypad = 1;
</td></tr>
<tr><td class="num" id="LN631">631</td><td class="line"> ((fpga_control_t *)&mask)->req_keypad = -1;
</td></tr>
<tr><td class="num" id="LN632">632</td><td class="line"> ((fpga_control_t *)&set)->keyrow = 1<<row;
</td></tr>
<tr><td class="num" id="LN633">633</td><td class="line"> ((fpga_control_t *)&mask)->keyrow = -1;
</td></tr>
<tr><td class="num" id="LN634">634</td><td class="line">
</td></tr>
<tr><td class="num" id="LN635">635</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN636">636</td><td class="line">
</td></tr>
<tr><td class="num" id="LN637">637</td><td class="line"> <span class='comment'>/* Update the global variable with the new settings. */</span>
</td></tr>
<tr><td class="num" id="LN638">638</td><td class="line"> FPGA_ctrl = set | (FPGA_ctrl & ~mask);
</td></tr>
<tr><td class="num" id="LN639">639</td><td class="line">
</td></tr>
<tr><td class="num" id="LN640">640</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN641">641</td><td class="line"> <span class='comment'>/* Now do the write to the control register. */</span>
</td></tr>
<tr><td class="num" id="LN642">642</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN643">643</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN644">644</td><td class="line">
</td></tr>
<tr><td class="num" id="LN645">645</td><td class="line"> <span class='comment'>/* Make sure that the Xbus is idle. */</span>
</td></tr>
<tr><td class="num" id="LN646">646</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN647">647</td><td class="line">
</td></tr>
<tr><td class="num" id="LN648">648</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN649">649</td><td class="line"> <span class='comment'>/* Extra read when XBUS is not busy. */</span>
</td></tr>
<tr><td class="num" id="LN650">650</td><td class="line"> rsp = PCI_Rd_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_STATUS_READ<span class='expansion'>0x0400</span></span>, 0);
</td></tr>
<tr><td class="num" id="LN651">651</td><td class="line"><span class='directive'>#else</span>
</td></tr>
<tr><td class="num" id="LN652">652</td><td class="line"> rsp = 0x0F000000;
</td></tr>
<tr><td class="num" id="LN653">653</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN654">654</td><td class="line">
</td></tr>
<tr><td class="num" id="LN655">655</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN656">656</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN657">657</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN658">658</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN659">659</td><td class="line"> <span class='comment'>/* Return the data read. */</span>
</td></tr>
<tr><td class="num" id="LN660">660</td><td class="line"> <span class='keyword'>return</span> (UINT8) (((fpga_status_t *) &rsp)->column);
</td></tr>
<tr><td class="num" id="LN661">661</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN662">662</td><td class="line">
</td></tr>
<tr><td class="num" id="LN663">663</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN664">664</td><td class="line"> <span class='comment'>* FPGA_Cept_Read</span>
</td></tr>
<tr><td class="num" id="LN665">665</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN666">666</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN667">667</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN668">668</td><td class="line"> <span class='comment'>* Read the CEPT's registers. The CEPT register will be an offset into the</span>
</td></tr>
<tr><td class="num" id="LN669">669</td><td class="line"> <span class='comment'>* CEPT register's memory-mapped interface.</span>
</td></tr>
<tr><td class="num" id="LN670">670</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN671">671</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN672">672</td><td class="line"> <span class='comment'>* UINT32 register - The register to read (must be between 0 and 255).</span>
</td></tr>
<tr><td class="num" id="LN673">673</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN674">674</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN675">675</td><td class="line"> <span class='comment'>* Returns the value read from the register.</span>
</td></tr>
<tr><td class="num" id="LN676">676</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN677">677</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN678">678</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN679">679</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN680">680</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN681">681</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN682">682</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN683">683</td><td class="line">fpga_cept_response_t FPGA_Cept_Read(UINT32 reg)
</td></tr>
<tr><td class="num" id="LN684">684</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN685">685</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN686">686</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN687">687</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN688">688</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN689">689</td><td class="line">
</td></tr>
<tr><td class="num" id="LN690">690</td><td class="line"> <span class='comment'>/* The request and response for the xbus. */</span>
</td></tr>
<tr><td class="num" id="LN691">691</td><td class="line"> UINT32 rsp, req = 0;
</td></tr>
<tr><td class="num" id="LN692">692</td><td class="line">
</td></tr>
<tr><td class="num" id="LN693">693</td><td class="line"> <span class='comment'>/* Initialize the update to make. */</span>
</td></tr>
<tr><td class="num" id="LN694">694</td><td class="line"> ((fpga_cept_request_t *)&req)->req_cept = 1;
</td></tr>
<tr><td class="num" id="LN695">695</td><td class="line"> ((fpga_cept_request_t *)&req)->data = reg;
</td></tr>
<tr><td class="num" id="LN696">696</td><td class="line">
</td></tr>
<tr><td class="num" id="LN697">697</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN698">698</td><td class="line"> <span class='comment'>/* Wait until the Xbus is idle before doing request. */</span>
</td></tr>
<tr><td class="num" id="LN699">699</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN700">700</td><td class="line">
</td></tr>
<tr><td class="num" id="LN701">701</td><td class="line"> <span class='comment'>/* Write the request. */</span>
</td></tr>
<tr><td class="num" id="LN702">702</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span> + <span class='macro'>FPGA_CEPT_WRITE_BASE<span class='expansion'>0x0C00</span></span> + reg * 4, req, 0);
</td></tr>
<tr><td class="num" id="LN703">703</td><td class="line">
</td></tr>
<tr><td class="num" id="LN704">704</td><td class="line"> <span class='comment'>/* Wait until the Xbus is idle before reading result. */</span>
</td></tr>
<tr><td class="num" id="LN705">705</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN706">706</td><td class="line">
</td></tr>
<tr><td class="num" id="LN707">707</td><td class="line"> <span class='comment'>/* Read CEPT register to latch data. */</span>
</td></tr>
<tr><td class="num" id="LN708">708</td><td class="line"> rsp = PCI_Rd_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span> + <span class='macro'>FPGA_CEPT_READ_BASE<span class='expansion'>0x0C00</span></span> + reg * 4, 0);
</td></tr>
<tr><td class="num" id="LN709">709</td><td class="line"><span class='directive'>#else</span>
</td></tr>
<tr><td class="num" id="LN710">710</td><td class="line"> rsp = 0;
</td></tr>
<tr><td class="num" id="LN711">711</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN712">712</td><td class="line">
</td></tr>
<tr><td class="num" id="LN713">713</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN714">714</td><td class="line"> <span class='comment'>/* Allow other tasks to run. */</span>
</td></tr>
<tr><td class="num" id="LN715">715</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN716">716</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN717">717</td><td class="line">
</td></tr>
<tr><td class="num" id="LN718">718</td><td class="line"> <span class='comment'>/* Return the data read. */</span>
</td></tr>
<tr><td class="num" id="LN719">719</td><td class="line"> <span class='keyword'>return</span> *(fpga_cept_response_t *) &rsp;
</td></tr>
<tr><td class="num" id="LN720">720</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN721">721</td><td class="line">
</td></tr>
<tr><td class="num" id="LN722">722</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN723">723</td><td class="line"> <span class='comment'>* FPGA_Cept_Write</span>
</td></tr>
<tr><td class="num" id="LN724">724</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN725">725</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN726">726</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN727">727</td><td class="line"> <span class='comment'>* Write to the CEPT's memory mapped registers.</span>
</td></tr>
<tr><td class="num" id="LN728">728</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN729">729</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN730">730</td><td class="line"> <span class='comment'>* UINT32 register - The register to read (must be between 0 and 255).</span>
</td></tr>
<tr><td class="num" id="LN731">731</td><td class="line"> <span class='comment'>* UINT8 data - The data byte to write to this register.</span>
</td></tr>
<tr><td class="num" id="LN732">732</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN733">733</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN734">734</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN735">735</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN736">736</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN737">737</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN738">738</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN739">739</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN740">740</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN741">741</td><td class="line"><span class='keyword'>void</span> FPGA_Cept_Write(UINT32 reg, UINT8 data)
</td></tr>
<tr><td class="num" id="LN742">742</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN743">743</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN744">744</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN745">745</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN746">746</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN747">747</td><td class="line">
</td></tr>
<tr><td class="num" id="LN748">748</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN749">749</td><td class="line"> <span class='comment'>/* Store the result of the status register read. */</span>
</td></tr>
<tr><td class="num" id="LN750">750</td><td class="line"> UINT32 rsp;
</td></tr>
<tr><td class="num" id="LN751">751</td><td class="line">
</td></tr>
<tr><td class="num" id="LN752">752</td><td class="line"> <span class='comment'>/* Wait until the Xbus is idle before requesting. */</span>
</td></tr>
<tr><td class="num" id="LN753">753</td><td class="line"> Fpga_Xbus_Busy_Wait();
</td></tr>
<tr><td class="num" id="LN754">754</td><td class="line">
</td></tr>
<tr><td class="num" id="LN755">755</td><td class="line"> <span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN756">756</td><td class="line"> <span class='comment'>* Write the CEPT data to the appropriate register (offset from base). Note</span>
</td></tr>
<tr><td class="num" id="LN757">757</td><td class="line"> <span class='comment'>* that each register takes 4 bytes in the address space (hence we have</span>
</td></tr>
<tr><td class="num" id="LN758">758</td><td class="line"> <span class='comment'>* to multiple the register by 4 to get the offset from the base register).</span>
</td></tr>
<tr><td class="num" id="LN759">759</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN760">760</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span> + <span class='macro'>FPGA_CEPT_WRITE_BASE<span class='expansion'>0x0C00</span></span> + reg * 4,
</td></tr>
<tr><td class="num" id="LN761">761</td><td class="line"> (UINT32) data, 0);
</td></tr>
<tr><td class="num" id="LN762">762</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN763">763</td><td class="line">
</td></tr>
<tr><td class="num" id="LN764">764</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN765">765</td><td class="line"> <span class='comment'>/* Allow other tasks to run. */</span>
</td></tr>
<tr><td class="num" id="LN766">766</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN767">767</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN768">768</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN769">769</td><td class="line">
</td></tr>
<tr><td class="num" id="LN770">770</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN771">771</td><td class="line"> <span class='comment'>* FPGA_Cept_Mux_Write</span>
</td></tr>
<tr><td class="num" id="LN772">772</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN773">773</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN774">774</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN775">775</td><td class="line"> <span class='comment'>* Update the CEPT mux with the new mask.</span>
</td></tr>
<tr><td class="num" id="LN776">776</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN777">777</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN778">778</td><td class="line"> <span class='comment'>* fpga_cept_mux_t set - The bits to set.</span>
</td></tr>
<tr><td class="num" id="LN779">779</td><td class="line"> <span class='comment'>* fpga_cept_mux_t clr - The bits to clr.</span>
</td></tr>
<tr><td class="num" id="LN780">780</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN781">781</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN782">782</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN783">783</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN784">784</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN785">785</td><td class="line"><span class='keyword'>void</span> FPGA_Cept_Mux_Write(fpga_cept_mux_t set, fpga_cept_mux_t clr)
</td></tr>
<tr><td class="num" id="LN786">786</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN787">787</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN788">788</td><td class="line"> <span class='comment'>/* Put the SH4 in supervisory mode to allow PCI to access memory. */</span>
</td></tr>
<tr><td class="num" id="LN789">789</td><td class="line"> <span class='macro'>NU_SUPERV_USER_VARIABLES<span class='expansion'>TC_TCB *__sud_thread_ptr = (TC_TCB*)(TCD_Current_Thread);</span></span>
</td></tr>
<tr><td class="num" id="LN790">790</td><td class="line"> <span class='macro'>NU_SUPERVISOR_MODE()<span class='expansion'>SUC_Supervisor_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN791">791</td><td class="line">
</td></tr>
<tr><td class="num" id="LN792">792</td><td class="line"> {
</td></tr>
<tr><td class="num" id="LN793">793</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN794">794</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN795">795</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN796">796</td><td class="line">
</td></tr>
<tr><td class="num" id="LN797">797</td><td class="line"> <span class='comment'>/* Update the global variable with the new settings. */</span>
</td></tr>
<tr><td class="num" id="LN798">798</td><td class="line"> FPGA_mux = set | (FPGA_mux & ~clr);
</td></tr>
<tr><td class="num" id="LN799">799</td><td class="line">
</td></tr>
<tr><td class="num" id="LN800">800</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN801">801</td><td class="line"> <span class='comment'>/* Write the request. */</span>
</td></tr>
<tr><td class="num" id="LN802">802</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CEPT_MUX_WRITE<span class='expansion'>0x1000</span></span>, FPGA_mux, 0);
</td></tr>
<tr><td class="num" id="LN803">803</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN804">804</td><td class="line">
</td></tr>
<tr><td class="num" id="LN805">805</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN806">806</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN807">807</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN808">808</td><td class="line"> }
</td></tr>
<tr><td class="num" id="LN809">809</td><td class="line">
</td></tr>
<tr><td class="num" id="LN810">810</td><td class="line"> <span class='comment'>/* Remember to return to user mode. */</span>
</td></tr>
<tr><td class="num" id="LN811">811</td><td class="line"> <span class='macro'>NU_USER_MODE()<span class='expansion'>SUC_User_Mode(__sud_thread_ptr)</span></span>;
</td></tr>
<tr><td class="num" id="LN812">812</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN813">813</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN814">814</td><td class="line">
</td></tr>
<tr><td class="num" id="LN815">815</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN816">816</td><td class="line"> <span class='comment'>* FPGA_LCD_Write</span>
</td></tr>
<tr><td class="num" id="LN817">817</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN818">818</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN819">819</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN820">820</td><td class="line"> <span class='comment'>* Write to the LCD's memory mapped registers.</span>
</td></tr>
<tr><td class="num" id="LN821">821</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN822">822</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN823">823</td><td class="line"> <span class='comment'>* BOOLEAN data_not_cmd - The value of the A0 bit (for Optrex display) will</span>
</td></tr>
<tr><td class="num" id="LN824">824</td><td class="line"> <span class='comment'>* be passed with this variable. This should be NU_TRUE for a data write</span>
</td></tr>
<tr><td class="num" id="LN825">825</td><td class="line"> <span class='comment'>* and NU_FALSE for a command write.</span>
</td></tr>
<tr><td class="num" id="LN826">826</td><td class="line"> <span class='comment'>* UINT8 data_byte - The command or data to write.</span>
</td></tr>
<tr><td class="num" id="LN827">827</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN828">828</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN829">829</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN830">830</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN831">831</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN832">832</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN833">833</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN834">834</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN835">835</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN836">836</td><td class="line"><span class='keyword'>void</span> FPGA_LCD_Write(BOOLEAN data_not_cmd, UINT8 data_byte)
</td></tr>
<tr><td class="num" id="LN837">837</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN838">838</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN839">839</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN840">840</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN841">841</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN842">842</td><td class="line"> <span class='comment'>/* The request and response for the xbus. */</span>
</td></tr>
<tr><td class="num" id="LN843">843</td><td class="line"> UINT32 rsp, req = 0;
</td></tr>
<tr><td class="num" id="LN844">844</td><td class="line">
</td></tr>
<tr><td class="num" id="LN845">845</td><td class="line"> <span class='comment'>/* Setup Xbus to read keypad's row. */</span>
</td></tr>
<tr><td class="num" id="LN846">846</td><td class="line"> ((fpga_lcd_t *)&req)->a0 = data_not_cmd;
</td></tr>
<tr><td class="num" id="LN847">847</td><td class="line"> ((fpga_lcd_t *)&req)->data = data_byte;
</td></tr>
<tr><td class="num" id="LN848">848</td><td class="line">
</td></tr>
<tr><td class="num" id="LN849">849</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN850">850</td><td class="line"> <span class='comment'>/* Make sure that xbus is idle before doing write. */</span>
</td></tr>
<tr><td class="num" id="LN851">851</td><td class="line"> <span class="mrange">Fpga_Xbus_Busy_Wait()</span>;
</td></tr>
<tr><td class="num"></td><td class="line"><div id="Path1" class="msg msgEvent" style="margin-left:5ex"><table class="msgT"><tr><td valign="top"><div class="PathIndex PathIndexEvent">1</div></td><td>Calling 'Fpga_Xbus_Busy_Wait'</td><td><div class="PathNav"><a href="#EndPath" title="Next event (2)">→</a></div></td></tr></table></div></td></tr>
<tr><td class="num" id="LN852">852</td><td class="line">
</td></tr>
<tr><td class="num" id="LN853">853</td><td class="line"> <span class='comment'>/* Write the request. */</span>
</td></tr>
<tr><td class="num" id="LN854">854</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_LCD_WRITE<span class='expansion'>0x0800</span></span>, req, 0);
</td></tr>
<tr><td class="num" id="LN855">855</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN856">856</td><td class="line">
</td></tr>
<tr><td class="num" id="LN857">857</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN858">858</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN859">859</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN860">860</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN861">861</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN862">862</td><td class="line">
</td></tr>
<tr><td class="num" id="LN863">863</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN864">864</td><td class="line"> <span class='comment'>* FPGA_USB1_Watch_Write</span>
</td></tr>
<tr><td class="num" id="LN865">865</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN866">866</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN867">867</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN868">868</td><td class="line"> <span class='comment'>* Function for writing the first USB watch address.</span>
</td></tr>
<tr><td class="num" id="LN869">869</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN870">870</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN871">871</td><td class="line"> <span class='comment'>* fpga_watch_t addr - The new value to write to the FPGA.</span>
</td></tr>
<tr><td class="num" id="LN872">872</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN873">873</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN874">874</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN875">875</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN876">876</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN877">877</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN878">878</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN879">879</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN880">880</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN881">881</td><td class="line"><span class='keyword'>void</span> FPGA_USB1_Watch_Write(fpga_watch_t addr)
</td></tr>
<tr><td class="num" id="LN882">882</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN883">883</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN884">884</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN885">885</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN886">886</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN887">887</td><td class="line">
</td></tr>
<tr><td class="num" id="LN888">888</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN889">889</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_USB1_WATCH<span class='expansion'>0x1800</span></span>, *(UINT32 *)&addr, 0);
</td></tr>
<tr><td class="num" id="LN890">890</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN891">891</td><td class="line">
</td></tr>
<tr><td class="num" id="LN892">892</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN893">893</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN894">894</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN895">895</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN896">896</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN897">897</td><td class="line">
</td></tr>
<tr><td class="num" id="LN898">898</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN899">899</td><td class="line"> <span class='comment'>* FPGA_USB2_Watch_Write</span>
</td></tr>
<tr><td class="num" id="LN900">900</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN901">901</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN902">902</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN903">903</td><td class="line"> <span class='comment'>* Function for writing the second USB watch address.</span>
</td></tr>
<tr><td class="num" id="LN904">904</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN905">905</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN906">906</td><td class="line"> <span class='comment'>* fpga_watch_t addr - The new value to write to the FPGA.</span>
</td></tr>
<tr><td class="num" id="LN907">907</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN908">908</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN909">909</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN910">910</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN911">911</td><td class="line"> <span class='comment'>* There can be no contention between other tasks that read the Xbus during</span>
</td></tr>
<tr><td class="num" id="LN912">912</td><td class="line"> <span class='comment'>* execution of this function. It is assumed that the caller is in</span>
</td></tr>
<tr><td class="num" id="LN913">913</td><td class="line"> <span class='comment'>* supervisory mode not user mode. This will crash and burn if not in</span>
</td></tr>
<tr><td class="num" id="LN914">914</td><td class="line"> <span class='comment'>* supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN915">915</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN916">916</td><td class="line"><span class='keyword'>void</span> FPGA_USB2_Watch_Write(fpga_watch_t addr)
</td></tr>
<tr><td class="num" id="LN917">917</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN918">918</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN919">919</td><td class="line"> <span class='comment'>/* Make sure we have no contention during access to PCI. */</span>
</td></tr>
<tr><td class="num" id="LN920">920</td><td class="line"> OPTION old_preempt = <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(<span class='macro'>NU_NO_PREEMPT<span class='expansion'>8</span></span>);
</td></tr>
<tr><td class="num" id="LN921">921</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN922">922</td><td class="line">
</td></tr>
<tr><td class="num" id="LN923">923</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN924">924</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_USB2_WATCH<span class='expansion'>0x1C00</span></span>, *(UINT32 *)&addr, 0);
</td></tr>
<tr><td class="num" id="LN925">925</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN926">926</td><td class="line">
</td></tr>
<tr><td class="num" id="LN927">927</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN928">928</td><td class="line"> <span class='comment'>/* Allow other tasks to read/write FPGA_cntl. */</span>
</td></tr>
<tr><td class="num" id="LN929">929</td><td class="line"> (<span class='keyword'>void</span>) <span class='macro'>NU_Change_Preemption<span class='expansion'>TCSE_Change_Preemption</span></span>(old_preempt);
</td></tr>
<tr><td class="num" id="LN930">930</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN931">931</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN932">932</td><td class="line">
</td></tr>
<tr><td class="num" id="LN933">933</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN934">934</td><td class="line"> <span class='comment'>* FPGA_Unlock_Nv, Lock_Nv</span>
</td></tr>
<tr><td class="num" id="LN935">935</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN936">936</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN937">937</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN938">938</td><td class="line"> <span class='comment'>* Unlocks or locks the NV ram (this should only be called when Nucleus is</span>
</td></tr>
<tr><td class="num" id="LN939">939</td><td class="line"> <span class='comment'>* not running).</span>
</td></tr>
<tr><td class="num" id="LN940">940</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN941">941</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN942">942</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN943">943</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN944">944</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN945">945</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN946">946</td><td class="line"> <span class='comment'>* These must be called when there is no application code running. This is</span>
</td></tr>
<tr><td class="num" id="LN947">947</td><td class="line"> <span class='comment'>* mainly used for Application_Initialize functions that have to lock and</span>
</td></tr>
<tr><td class="num" id="LN948">948</td><td class="line"> <span class='comment'>* unlock memory (i.e., see GlobalNV_Init).</span>
</td></tr>
<tr><td class="num" id="LN949">949</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN950">950</td><td class="line"><span class='keyword'>void</span> FPGA_Unlock_Nv(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN951">951</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN952">952</td><td class="line"> <span class='comment'>/* Clear D23. */</span>
</td></tr>
<tr><td class="num" id="LN953">953</td><td class="line"> FPGA_ctrl &= ~ 0x00800000;
</td></tr>
<tr><td class="num" id="LN954">954</td><td class="line">
</td></tr>
<tr><td class="num" id="LN955">955</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN956">956</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN957">957</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN958">958</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN959">959</td><td class="line"><span class='keyword'>void</span> FPGA_Lock_Nv(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN960">960</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN961">961</td><td class="line"> <span class='comment'>/* Set D23. */</span>
</td></tr>
<tr><td class="num" id="LN962">962</td><td class="line"> FPGA_ctrl |= 0x00800000;
</td></tr>
<tr><td class="num" id="LN963">963</td><td class="line">
</td></tr>
<tr><td class="num" id="LN964">964</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN965">965</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN966">966</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN967">967</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN968">968</td><td class="line">
</td></tr>
<tr><td class="num" id="LN969">969</td><td class="line"><span class='comment'>/*</span>
</td></tr>
<tr><td class="num" id="LN970">970</td><td class="line"> <span class='comment'>* FPGA_Initialize</span>
</td></tr>
<tr><td class="num" id="LN971">971</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN972">972</td><td class="line"> <span class='comment'>***Description**************************************************************</span>
</td></tr>
<tr><td class="num" id="LN973">973</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN974">974</td><td class="line"> <span class='comment'>* Initializes any Nucleus structures needed for the FPGA. This also sets</span>
</td></tr>
<tr><td class="num" id="LN975">975</td><td class="line"> <span class='comment'>* the FPGA control to a known state.</span>
</td></tr>
<tr><td class="num" id="LN976">976</td><td class="line"> <span class='comment'>***Parameters***************************************************************</span>
</td></tr>
<tr><td class="num" id="LN977">977</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN978">978</td><td class="line"> <span class='comment'>***Results******************************************************************</span>
</td></tr>
<tr><td class="num" id="LN979">979</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN980">980</td><td class="line"> <span class='comment'>***Notes********************************************************************</span>
</td></tr>
<tr><td class="num" id="LN981">981</td><td class="line"> <span class='comment'>*</span>
</td></tr>
<tr><td class="num" id="LN982">982</td><td class="line"> <span class='comment'>* This will crash and burn if not in supervisory mode!</span>
</td></tr>
<tr><td class="num" id="LN983">983</td><td class="line"> <span class='comment'>*/</span>
</td></tr>
<tr><td class="num" id="LN984">984</td><td class="line"><span class='keyword'>void</span> FPGA_Initialize(<span class='keyword'>void</span>)
</td></tr>
<tr><td class="num" id="LN985">985</td><td class="line">{
</td></tr>
<tr><td class="num" id="LN986">986</td><td class="line"> FPGA_unlock_bitmap.lock_memory = 0;
</td></tr>
<tr><td class="num" id="LN987">987</td><td class="line"> FPGA_lock_bitmap.lock_memory = 1;
</td></tr>
<tr><td class="num" id="LN988">988</td><td class="line"> FPGA_mask_bitmap.lock_memory = -1;
</td></tr>
<tr><td class="num" id="LN989">989</td><td class="line">
</td></tr>
<tr><td class="num" id="LN990">990</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN991">991</td><td class="line"> <span class='comment'>/* Create a semaphore for the FPGA accesses. */</span>
</td></tr>
<tr><td class="num" id="LN992">992</td><td class="line"> <span class='macro'>NU_Create_Semaphore<span class='expansion'>SMCE_Create_Semaphore</span></span>(&FPGA_sem, <span class='string_literal'>"FPGA_SEM"</span>, 1, <span class='macro'>NU_FIFO<span class='expansion'>6</span></span>);
</td></tr>
<tr><td class="num" id="LN993">993</td><td class="line">
</td></tr>
<tr><td class="num" id="LN994">994</td><td class="line"> <span class='comment'>/* Create a semaphore for protecting the LOADBATT Control Line */</span>
</td></tr>
<tr><td class="num" id="LN995">995</td><td class="line"> <span class='macro'>NU_Create_Semaphore<span class='expansion'>SMCE_Create_Semaphore</span></span>(&FPGA_batt_sem, <span class='string_literal'>"FPGABATT"</span>, 1, <span class='macro'>NU_FIFO<span class='expansion'>6</span></span>);
</td></tr>
<tr><td class="num" id="LN996">996</td><td class="line"> FPGA_battload_count = 0;
</td></tr>
<tr><td class="num" id="LN997">997</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN998">998</td><td class="line">
</td></tr>
<tr><td class="num" id="LN999">999</td><td class="line"> <span class='comment'>/* Initialize the NV ram control global varaible and PCI register. */</span>
</td></tr>
<tr><td class="num" id="LN1000">1000</td><td class="line"> *(fpga_control_t *) &FPGA_ctrl = FPGA_lock_bitmap;
</td></tr>
<tr><td class="num" id="LN1001">1001</td><td class="line"> ((fpga_control_t *) &FPGA_ctrl)->vbatt_en = 1;
</td></tr>
<tr><td class="num" id="LN1002">1002</td><td class="line">
</td></tr>
<tr><td class="num" id="LN1003">1003</td><td class="line"><span class='directive'>#ifdef NUCLEUS</span>
</td></tr>
<tr><td class="num" id="LN1004">1004</td><td class="line"> ((fpga_control_t *) &FPGA_ctrl)->lcd_intensity = GlobalNV.Ui_lcd_brightness;
</td></tr>
<tr><td class="num" id="LN1005">1005</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN1006">1006</td><td class="line">
</td></tr>
<tr><td class="num" id="LN1007">1007</td><td class="line"><span class='directive'>#ifndef SOLUTION_ENGINE</span>
</td></tr>
<tr><td class="num" id="LN1008">1008</td><td class="line"> (<span class='keyword'>void</span>) PCI_Wr_Mem_Long(<span class='macro'>FPGA_PCI_MEM_ADDR<span class='expansion'>0x00C00000</span></span>+<span class='macro'>FPGA_CONTROL_WRITE<span class='expansion'>0x0400</span></span>, FPGA_ctrl, 0);
</td></tr>
<tr><td class="num" id="LN1009">1009</td><td class="line"><span class='directive'>#endif</span>
</td></tr>
<tr><td class="num" id="LN1010">1010</td><td class="line">}
</td></tr>
<tr><td class="num" id="LN1011">1011</td><td class="line">
</td></tr>
<tr><td class="num" id="LN1012">1012</td><td class="line">
</td></tr>
</table></body></html>