[cfe-dev] FYI, Intel folks might be looking to add the __iso_volatile_Xxx family for MSVC STL <atomic> soon

Billy O'Neal (VC LIBS) via cfe-dev cfe-dev at lists.llvm.org
Thu Mar 28 14:18:08 PDT 2019


>  It reads as, "do an ISO C++ standard volatile load"

That is the intended behavior.

> it really means "do an atomic (not volatile) load"

Only if that happens to be the case on the indicated hardware. For example, MSVC++ implements seq_cst loads on ARM with an __iso_volatile_load## followed by __dmb. It only gets atomic behavior on x86 because a seq_cst load on that hardware is an ordinary load.

__iso_volatile_store is also affected, though the specific customer bug report that opened this can of worms doesn't touch that.

Thanks for your help!

Billy3
________________________________
From: Reid Kleckner <rnk at google.com>
Sent: Thursday, March 28, 2019 02:14 PM
To: JF Bastien
Cc: Billy O'Neal (VC LIBS); cfe-dev
Subject: Re: [cfe-dev] FYI, Intel folks might be looking to add the __iso_volatile_Xxx family for MSVC STL <atomic> soon

On Thu, Mar 28, 2019 at 1:46 PM JF Bastien <jfbastien at apple.com<mailto:jfbastien at apple.com>> wrote:
On Mar 28, 2019, at 12:02 PM, Billy O'Neal (VC LIBS) <bion at microsoft.com<mailto:bion at microsoft.com>> wrote:

Update: VS2019 Update 2 is likely to do this; who do I need to prod such that I get to use these unconditionally in our <atomic> ?🙂

You want the same feature in clang-cl, so I suggest talking to Reid, sending a patch to clang, and having him review it ;-)

I think it's just a matter of moving code from BuiltinsAArch64.def<https://nam06.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fllvm%2Fllvm-project%2Fblob%2Fmaster%2Fclang%2Finclude%2Fclang%2FBasic%2FBuiltinsAArch64.def%23L82&data=02%7C01%7Cbion%40microsoft.com%7Cf794057fb30f4989fdeb08d6b3c268aa%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C1%7C636894044906044641&sdata=nrge3My1Gn0Qz1%2Bbe7C2LF5PodSwlCU%2B0D4Xd0Hg0p4%3D&reserved=0> (and ARM) to Builtins.def, and maybe some followon changes.

The naming for these intrinsics is confusing. It reads as, "do an ISO C++ standard volatile load", but it really means "do an atomic (not volatile) load", but I suppose the time to address that is long gone.

I went ahead and started a patch to make them available.
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