[cfe-dev] [llvm-dev] generate vectorized code

Mehdi Amini via cfe-dev cfe-dev at lists.llvm.org
Fri Mar 18 16:26:20 PDT 2016


> On Mar 18, 2016, at 4:19 PM, Rail Shafigulin <rail at esenciatech.com> wrote:
> 
> 
> 
> On Fri, Mar 18, 2016 at 4:16 PM, Mehdi Amini <mehdi.amini at apple.com <mailto:mehdi.amini at apple.com>> wrote:
> 
>> On Mar 18, 2016, at 4:14 PM, Rail Shafigulin <rail at esenciatech.com <mailto:rail at esenciatech.com>> wrote:
>> 
>> Here is how I started with SelectionDAG: 
>> 
>> - small IR (bugpoint can help)
>> Did you mean a break point? 
> 
> No I really meant bugpoint: http://llvm.org/docs/Bugpoint.html <http://llvm.org/docs/Bugpoint.html>
> 
>> 
>> - the magic flag: -debug 
>> - read the output of SelectionDAG debugging (especially with cycles)
>> - matching the log to source code
>> What log are you talking about?
> 
> llc -debug mentioned above.
> What do you mean by matching a log to source? What log are you talking about? 

I'm talking about this:


$ cat <<EOF | ../ninja-clang-release/bin/clang -x c - -emit-llvm -S -o - -O3 | ../ninja-clang-release/bin/llc -debug 2>&1 | grep -i combining -C 20
> void foo (int a1, int a2, int a3, int a4, int b1, int b2, int b3, int b4, int *res) {
>   res[0] = a1 + b1 * 2;
>   res[1] = a2 + b2 * 2;
>   res[2] = a3 + b3 * 2;
>   res[3] = a4 + b4 * 2;
> }
> EOF
...
...
=== foo
Initial selection DAG: BB#0 'foo:entry'
SelectionDAG has 43 nodes:
  t0: ch = EntryToken
  t21: i32 = Constant<0>
  t27: i32 = Constant<2>
  t30: i32 = Constant<3>
                t2: i32,ch = CopyFromReg t0, Register:i32 %vreg0
              t35: v4i32 = insert_vector_elt undef:v4i32, t2, Constant:i64<0>
              t4: i32,ch = CopyFromReg t0, Register:i32 %vreg1
            t36: v4i32 = insert_vector_elt t35, t4, Constant:i64<1>
            t6: i32,ch = CopyFromReg t0, Register:i32 %vreg2
          t37: v4i32 = insert_vector_elt t36, t6, Constant:i64<2>
          t8: i32,ch = CopyFromReg t0, Register:i32 %vreg3
        t38: v4i32 = insert_vector_elt t37, t8, Constant:i64<3>
                  t10: i32,ch = CopyFromReg t0, Register:i32 %vreg4
                t23: v4i32 = insert_vector_elt undef:v4i32, t10, Constant:i64<0>
                t12: i32,ch = CopyFromReg t0, Register:i32 %vreg5
              t26: v4i32 = insert_vector_elt t23, t12, Constant:i64<1>
              t15: i32,ch = load<LD4[FixedStack-1]> t0, FrameIndex:i64<-1>, undef:i64
            t29: v4i32 = insert_vector_elt t26, t15, Constant:i64<2>
            t17: i32,ch = load<LD4[FixedStack-2]> t0, FrameIndex:i64<-2>, undef:i64
          t32: v4i32 = insert_vector_elt t29, t17, Constant:i64<3>
          t33: v4i32 = BUILD_VECTOR Constant:i32<1>, Constant:i32<1>, Constant:i32<1>, Constant:i32<1>
        t34: v4i32 = shl t32, t33
      t39: v4i32 = add t38, t34
      t19: i64,ch = load<LD8[FixedStack-3]> t0, FrameIndex:i64<-3>, undef:i64
    t40: ch = store<ST16[%10](align=4)(tbaa=<0x7fd81b503a58>)> t0, t39, t19, undef:i64
  t42: ch = X86ISD::RET_FLAG t40, TargetConstant:i16<0>



Combining: t42: ch = X86ISD::RET_FLAG t40, TargetConstant:i16<0>

Combining: t41: i16 = TargetConstant<0>

Combining: t40: ch = store<ST16[%10](align=4)(tbaa=<0x7fd81b503a58>)> t0, t39, t19, undef:i64

Combining: t39: v4i32 = add t38, t34

Combining: t38: v4i32 = insert_vector_elt t37, t8, Constant:i64<3>

Combining: t37: v4i32 = insert_vector_elt t36, t6, Constant:i64<2>

Combining: t36: v4i32 = insert_vector_elt t35, t4, Constant:i64<1>

Combining: t35: v4i32 = insert_vector_elt undef:v4i32, t2, Constant:i64<0>
 ... into: t44: v4i32 = BUILD_VECTOR t2, undef:i32, undef:i32, undef:i32

Combining: t36: v4i32 = insert_vector_elt t44, t4, Constant:i64<1>
 ... into: t45: v4i32 = BUILD_VECTOR t2, t4, undef:i32, undef:i32


...

..
...


Legalizing: t53: v4i32 = BUILD_VECTOR t10, t12, t15, t17
 ... replacing: t53: v4i32 = BUILD_VECTOR t10, t12, t15, t17
     with:      t61: v4i32 = vector_shuffle<0,4,1,5> t59, t60

Legalizing: t47: v4i32 = BUILD_VECTOR t2, t4, t6, t8
 ... replacing: t47: v4i32 = BUILD_VECTOR t2, t4, t6, t8
     with:      t68: v4i32 = vector_shuffle<0,4,1,5> t66, t67



This is exactly what happens in SelectionDAG, and matching these messages to the source code should help figuring what SelectionDAG is doing and why.

-- 
Mehdi


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/cfe-dev/attachments/20160318/c172437b/attachment-0001.html>


More information about the cfe-dev mailing list