<div dir="ltr">Reverted in 3761b9a2345aff197707d23a68d4a178489f60e4 for now.</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, May 6, 2021 at 9:58 AM Nico Weber <<a href="mailto:thakis@chromium.org">thakis@chromium.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Looks like this breaks tests: <a href="http://45.33.8.238/linux/45985/step_7.txt" target="_blank">http://45.33.8.238/linux/45985/step_7.txt</a> , <a href="https://lab.llvm.org/buildbot/#/builders/139/builds/3818" target="_blank">https://lab.llvm.org/buildbot/#/builders/139/builds/3818</a><div><br></div><div>(Is there a phab link for this?)</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, May 6, 2021 at 9:37 AM Nemanja Ivanovic via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org" target="_blank">cfe-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Nemanja Ivanovic<br>
Date: 2021-05-06T08:37:36-05:00<br>
New Revision: ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/ed87f512bb9eb5c1d44e9a1182ffeaf23d6c5ae8.diff</a><br>
<br>
LOG: [PowerPC] Provide some P8-specific altivec overloads for P7<br>
<br>
This adds additional support for XL compatibility. There are a number<br>
of functions in altivec.h that produce a single instruction (or a<br>
very short sequence) for Power8 but can be done on Power7 without<br>
scalarization. XL provides these implementations.<br>
This patch adds the following overloads for doubleword vectors:<br>
vec_add<br>
vec_cmpeq<br>
vec_cmpgt<br>
vec_cmpge<br>
vec_cmplt<br>
vec_cmple<br>
vec_sl<br>
vec_sr<br>
vec_sra<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
clang/lib/Headers/altivec.h<br>
clang/test/CodeGen/builtins-ppc-vsx.c<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h<br>
index cb4f35caf4d4b..0441c57e3da28 100644<br>
--- a/clang/lib/Headers/altivec.h<br>
+++ b/clang/lib/Headers/altivec.h<br>
@@ -309,6 +309,26 @@ static __inline__ vector unsigned char __attribute__((__always_inline__))<br>
vec_add_u128(vector unsigned char __a, vector unsigned char __b) {<br>
return __builtin_altivec_vadduqm(__a, __b);<br>
}<br>
+#elif defined(__VSX__)<br>
+static __inline__ vector signed long long __ATTRS_o_ai<br>
+vec_add(vector signed long long __a, vector signed long long __b) {<br>
+ vector unsigned int __res =<br>
+ (vector unsigned int)__a + (vector unsigned int)__b;<br>
+ vector unsigned int __carry = __builtin_altivec_vaddcuw(<br>
+ (vector unsigned int)__a, (vector unsigned int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __carry = __builtin_shufflevector(__carry, __carry, 3, 0, 1, 2);<br>
+#else<br>
+ __carry = __builtin_shufflevector(__carry, __carry, 1, 2, 3, 0);<br>
+#endif<br>
+ return (vector signed long long)(__res + __carry);<br>
+}<br>
+<br>
+static __inline__ vector unsigned long long __ATTRS_o_ai<br>
+vec_add(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ return (vector unsigned long long)vec_add((vector signed long long)__a,<br>
+ (vector signed long long)__b);<br>
+}<br>
#endif // defined(__POWER8_VECTOR__) && defined(__powerpc64__)<br>
<br>
static __inline__ vector float __ATTRS_o_ai vec_add(vector float __a,<br>
@@ -1730,7 +1750,31 @@ vec_cmpeq(vector bool long long __a, vector bool long long __b) {<br>
return (vector bool long long)__builtin_altivec_vcmpequd(<br>
(vector long long)__a, (vector long long)__b);<br>
}<br>
+#else<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpeq(vector signed long long __a, vector signed long long __b) {<br>
+ vector bool int __wordcmp =<br>
+ vec_cmpeq((vector signed int)__a, (vector signed int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __wordcmp &= __builtin_shufflevector(__wordcmp, __wordcmp, 3, 0, 1, 2);<br>
+ return (vector bool long long)__builtin_shufflevector(__wordcmp, __wordcmp, 1,<br>
+ 1, 3, 3);<br>
+#else<br>
+ __wordcmp &= __builtin_shufflevector(__wordcmp, __wordcmp, 1, 2, 3, 0);<br>
+ return (vector bool long long)__builtin_shufflevector(__wordcmp, __wordcmp, 0,<br>
+ 0, 2, 2);<br>
+#endif<br>
+}<br>
<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpeq(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ return vec_cmpeq((vector signed long long)__a, (vector signed long long)__b);<br>
+}<br>
+<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpeq(vector bool long long __a, vector bool long long __b) {<br>
+ return vec_cmpeq((vector signed long long)__a, (vector signed long long)__b);<br>
+}<br>
#endif<br>
<br>
static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector float __a,<br>
@@ -2018,6 +2062,24 @@ vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {<br>
return (vector bool long long)<br>
~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long long)__b));<br>
}<br>
+#else<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpne(vector bool long long __a, vector bool long long __b) {<br>
+ return (vector bool long long)~(<br>
+ vec_cmpeq((vector signed long long)__a, (vector signed long long)__b));<br>
+}<br>
+<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpne(vector signed long long __a, vector signed long long __b) {<br>
+ return (vector bool long long)~(<br>
+ vec_cmpeq((vector signed long long)__a, (vector signed long long)__b));<br>
+}<br>
+<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ return (vector bool long long)~(<br>
+ vec_cmpeq((vector signed long long)__a, (vector signed long long)__b));<br>
+}<br>
#endif<br>
<br>
#ifdef __VSX__<br>
@@ -2070,6 +2132,46 @@ static __inline__ vector bool long long __ATTRS_o_ai<br>
vec_cmpgt(vector unsigned long long __a, vector unsigned long long __b) {<br>
return (vector bool long long)__builtin_altivec_vcmpgtud(__a, __b);<br>
}<br>
+#else<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpgt(vector signed long long __a, vector signed long long __b) {<br>
+ vector signed int __sgtw =<br>
+ vec_cmpgt((vector signed int)__a, (vector signed int)__b);<br>
+ vector unsigned int __ugtw =<br>
+ vec_cmpgt((vector unsigned int)__a, (vector unsigned int)__b);<br>
+ vector bool int __eqw =<br>
+ vec_cmpeq((vector signed int)__a, (vector signed int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __ugtw = __builtin_shufflevector(__ugtw, __ugtw, 3, 0, 1, 2) & __eqw;<br>
+ __sgtw |= (vector signed int)__ugtw;<br>
+ return (vector bool long long)__builtin_shufflevector(__sgtw, __sgtw, 1, 1, 3,<br>
+ 3);<br>
+#else<br>
+ __ugtw = __builtin_shufflevector(__ugtw, __ugtw, 1, 2, 3, 0) & __eqw;<br>
+ __sgtw |= (vector signed int)__ugtw;<br>
+ return (vector bool long long)__builtin_shufflevector(__sgtw, __sgtw, 0, 0, 2,<br>
+ 2);<br>
+#endif<br>
+}<br>
+<br>
+static __inline__ vector bool long long __ATTRS_o_ai<br>
+vec_cmpgt(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ vector unsigned int __ugtw =<br>
+ vec_cmpgt((vector unsigned int)__a, (vector unsigned int)__b);<br>
+ vector bool int __eqw =<br>
+ vec_cmpeq((vector signed int)__a, (vector signed int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __eqw = __builtin_shufflevector(__ugtw, __ugtw, 3, 0, 1, 2) & __eqw;<br>
+ __ugtw |= __eqw;<br>
+ return (vector bool long long)__builtin_shufflevector(__ugtw, __ugtw, 1, 1, 3,<br>
+ 3);<br>
+#else<br>
+ __eqw = __builtin_shufflevector(__ugtw, __ugtw, 1, 2, 3, 0) & __eqw;<br>
+ __ugtw |= __eqw;<br>
+ return (vector bool long long)__builtin_shufflevector(__ugtw, __ugtw, 0, 0, 2,<br>
+ 2);<br>
+#endif<br>
+}<br>
#endif<br>
<br>
static __inline__ vector bool int __ATTRS_o_ai vec_cmpgt(vector float __a,<br>
@@ -2150,7 +2252,6 @@ vec_cmpge(vector double __a, vector double __b) {<br>
}<br>
#endif<br>
<br>
-#ifdef __POWER8_VECTOR__<br>
static __inline__ vector bool long long __ATTRS_o_ai<br>
vec_cmpge(vector signed long long __a, vector signed long long __b) {<br>
return ~(vec_cmpgt(__b, __a));<br>
@@ -2160,7 +2261,6 @@ static __inline__ vector bool long long __ATTRS_o_ai<br>
vec_cmpge(vector unsigned long long __a, vector unsigned long long __b) {<br>
return ~(vec_cmpgt(__b, __a));<br>
}<br>
-#endif<br>
<br>
#if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)<br>
static __inline__ vector bool __int128 __ATTRS_o_ai<br>
@@ -2274,7 +2374,6 @@ vec_cmple(vector double __a, vector double __b) {<br>
}<br>
#endif<br>
<br>
-#ifdef __POWER8_VECTOR__<br>
static __inline__ vector bool long long __ATTRS_o_ai<br>
vec_cmple(vector signed long long __a, vector signed long long __b) {<br>
return vec_cmpge(__b, __a);<br>
@@ -2284,7 +2383,6 @@ static __inline__ vector bool long long __ATTRS_o_ai<br>
vec_cmple(vector unsigned long long __a, vector unsigned long long __b) {<br>
return vec_cmpge(__b, __a);<br>
}<br>
-#endif<br>
<br>
#if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)<br>
static __inline__ vector bool __int128 __ATTRS_o_ai<br>
@@ -2354,7 +2452,6 @@ vec_cmplt(vector unsigned __int128 __a, vector unsigned __int128 __b) {<br>
}<br>
#endif<br>
<br>
-#ifdef __POWER8_VECTOR__<br>
static __inline__ vector bool long long __ATTRS_o_ai<br>
vec_cmplt(vector signed long long __a, vector signed long long __b) {<br>
return vec_cmpgt(__b, __a);<br>
@@ -2365,6 +2462,7 @@ vec_cmplt(vector unsigned long long __a, vector unsigned long long __b) {<br>
return vec_cmpgt(__b, __a);<br>
}<br>
<br>
+#ifdef __POWER8_VECTOR__<br>
/* vec_popcnt */<br>
<br>
static __inline__ vector signed char __ATTRS_o_ai<br>
@@ -8725,6 +8823,46 @@ vec_sl(vector unsigned long long __a, vector unsigned long long __b) {<br>
__CHAR_BIT__));<br>
}<br>
<br>
+static __inline__ vector long long __ATTRS_o_ai<br>
+vec_sl(vector long long __a, vector unsigned long long __b) {<br>
+ return (vector long long)vec_sl((vector unsigned long long)__a, __b);<br>
+}<br>
+#else<br>
+static __inline__ vector unsigned char __ATTRS_o_ai<br>
+vec_vspltb(vector unsigned char __a, unsigned char __b);<br>
+static __inline__ vector unsigned long long __ATTRS_o_ai<br>
+vec_sl(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ __b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);<br>
+<br>
+ // Big endian element one (the right doubleword) can be left shifted as-is.<br>
+ // The other element needs to be swapped into the right doubleword and<br>
+ // shifted. Then the right doublewords of the two result vectors are merged.<br>
+ vector signed long long __rightelt =<br>
+ (vector signed long long)__builtin_altivec_vslo((vector signed int)__a,<br>
+ (vector signed int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __rightelt = (vector signed long long)__builtin_altivec_vsl(<br>
+ (vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 0));<br>
+#else<br>
+ __rightelt = (vector signed long long)__builtin_altivec_vsl(<br>
+ (vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 15));<br>
+#endif<br>
+ __a = __builtin_shufflevector(__a, __a, 1, 0);<br>
+ __b = __builtin_shufflevector(__b, __b, 1, 0);<br>
+ vector signed long long __leftelt =<br>
+ (vector signed long long)__builtin_altivec_vslo((vector signed int)__a,<br>
+ (vector signed int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __leftelt = (vector signed long long)__builtin_altivec_vsl(<br>
+ (vector signed int)__leftelt, vec_vspltb((vector unsigned char)__b, 0));<br>
+ return __builtin_shufflevector(__rightelt, __leftelt, 0, 2);<br>
+#else<br>
+ __leftelt = (vector signed long long)__builtin_altivec_vsl(<br>
+ (vector signed int)__leftelt, vec_vspltb((vector unsigned char)__b, 15));<br>
+ return __builtin_shufflevector(__leftelt, __rightelt, 1, 3);<br>
+#endif<br>
+}<br>
+<br>
static __inline__ vector long long __ATTRS_o_ai<br>
vec_sl(vector long long __a, vector unsigned long long __b) {<br>
return (vector long long)vec_sl((vector unsigned long long)__a, __b);<br>
@@ -10190,6 +10328,47 @@ vec_sr(vector unsigned long long __a, vector unsigned long long __b) {<br>
__CHAR_BIT__));<br>
}<br>
<br>
+static __inline__ vector long long __ATTRS_o_ai<br>
+vec_sr(vector long long __a, vector unsigned long long __b) {<br>
+ return (vector long long)vec_sr((vector unsigned long long)__a, __b);<br>
+}<br>
+#else<br>
+static __inline__ vector unsigned long long __ATTRS_o_ai<br>
+vec_sr(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ __b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);<br>
+<br>
+ // Big endian element zero (the left doubleword) can be right shifted as-is.<br>
+ // However the shift amount must be in the right doubleword.<br>
+ // The other element needs to be swapped into the left doubleword and<br>
+ // shifted. Then the left doublewords of the two result vectors are merged.<br>
+ vector signed long long __swapshift = __builtin_shufflevector(__b, __b, 1, 0);<br>
+ vector signed long long __leftelt =<br>
+ (vector signed long long)__builtin_altivec_vsro((vector signed int)__a,<br>
+ __swapshift);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __leftelt = (vector signed long long)__builtin_altivec_vsr(<br>
+ (vector signed int)__leftelt,<br>
+ vec_vspltb((vector unsigned char)__swapshift, 0));<br>
+#else<br>
+ __leftelt = (vector signed long long)__builtin_altivec_vsr(<br>
+ (vector signed int)__leftelt,<br>
+ vec_vspltb((vector unsigned char)__swapshift, 15));<br>
+#endif<br>
+ __a = __builtin_shufflevector(__a, __a, 1, 0);<br>
+ vector signed long long __rightelt =<br>
+ (vector signed long long)__builtin_altivec_vsro((vector signed int)__a,<br>
+ (vector signed int)__b);<br>
+#ifdef __LITTLE_ENDIAN__<br>
+ __rightelt = (vector signed long long)__builtin_altivec_vsr(<br>
+ (vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 0));<br>
+ return __builtin_shufflevector(__rightelt, __leftelt, 1, 3);<br>
+#else<br>
+ __rightelt = (vector signed long long)__builtin_altivec_vsr(<br>
+ (vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 15));<br>
+ return __builtin_shufflevector(__leftelt, __rightelt, 0, 2);<br>
+#endif<br>
+}<br>
+<br>
static __inline__ vector long long __ATTRS_o_ai<br>
vec_sr(vector long long __a, vector unsigned long long __b) {<br>
return (vector long long)vec_sr((vector unsigned long long)__a, __b);<br>
@@ -10280,6 +10459,18 @@ static __inline__ vector unsigned long long __ATTRS_o_ai<br>
vec_sra(vector unsigned long long __a, vector unsigned long long __b) {<br>
return (vector unsigned long long)((vector signed long long)__a >> __b);<br>
}<br>
+#else<br>
+static __inline__ vector signed long long __ATTRS_o_ai<br>
+vec_sra(vector signed long long __a, vector unsigned long long __b) {<br>
+ __b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);<br>
+ return __a >> __b;<br>
+}<br>
+<br>
+static __inline__ vector unsigned long long __ATTRS_o_ai<br>
+vec_sra(vector unsigned long long __a, vector unsigned long long __b) {<br>
+ __b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);<br>
+ return (vector unsigned long long)((vector signed long long)__a >> __b);<br>
+}<br>
#endif<br>
<br>
/* vec_vsrab */<br>
<br>
diff --git a/clang/test/CodeGen/builtins-ppc-vsx.c b/clang/test/CodeGen/builtins-ppc-vsx.c<br>
index ecae9a620e426..4bb7a05a435a2 100644<br>
--- a/clang/test/CodeGen/builtins-ppc-vsx.c<br>
+++ b/clang/test/CodeGen/builtins-ppc-vsx.c<br>
@@ -2313,3 +2313,282 @@ vector double test_rsqrtd(vector double a, vector double b) {<br>
// CHECK-LE: fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00><br>
return vec_rsqrt(a);<br>
}<br>
+<br>
+void test_p8overloads_backwards_compat() {<br>
+ // CHECK-LABEL: test_p8overloads_backwards_compat<br>
+ res_vsll = vec_add(vsll, vsll);<br>
+ // CHECK: add <4 x i32><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: add <4 x i32><br>
+ // CHECK-LE: add <4 x i32><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vaddcuw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: add <4 x i32><br>
+ res_vull = vec_add(vull, vull);<br>
+ // CHECK: add <4 x i32><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: add <4 x i32><br>
+ // CHECK-LE: add <4 x i32><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vaddcuw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: add <4 x i32><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vbll = vec_cmpeq(vsll, vsll);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ res_vbll = vec_cmpeq(vull, vull);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ res_vbll = vec_cmpeq(vbll, vbll);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vbll = vec_cmpgt(vsll, vsll);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ res_vbll = vec_cmpgt(vull, vull);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vbll = vec_cmpge(vsll, vsll);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ // CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ res_vbll = vec_cmpge(vull, vull);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ // CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vbll = vec_cmplt(vsll, vsll);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ res_vbll = vec_cmplt(vull, vull);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vbll = vec_cmple(vsll, vsll);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ // CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ res_vbll = vec_cmple(vull, vull);<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0><br>
+ // CHECK: and <4 x i32><br>
+ // CHECK: or <4 x i32><br>
+ // CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2><br>
+ // CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw<br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2><br>
+ // CHECK-LE: and <4 x i32><br>
+ // CHECK-LE: or <4 x i32><br>
+ // CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3><br>
+ // CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vsll = vec_sl(vsll, vull);<br>
+ // CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3><br>
+ // CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2><br>
+ res_vull = vec_sl(vull, vull);<br>
+ // CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3><br>
+ // CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vsll = vec_sr(vsll, vull);<br>
+ // CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2><br>
+ // CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3><br>
+ res_vull = vec_sr(vull, vull);<br>
+ // CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2><br>
+ // CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0><br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro<br>
+ // CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr<br>
+ // CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3><br>
+ dummy();<br>
+ // CHECK: call void @dummy()<br>
+ // CHECK-LE: call void @dummy()<br>
+<br>
+ res_vsll = vec_sra(vsll, vull);<br>
+ // CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK: ashr <2 x i64><br>
+ // CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK-LE: ashr <2 x i64><br>
+ res_vull = vec_sra(vull, vull);<br>
+ // CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK: ashr <2 x i64><br>
+ // CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64><br>
+ // CHECK-LE: ashr <2 x i64><br>
+}<br>
<br>
<br>
<br>
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</blockquote></div>
</blockquote></div>