<div dir="ltr">It looks like the test fails everywhere: <a href="http://lab.llvm.org:8011/#/console">http://lab.llvm.org:8011/#/console</a><div><br></div><div>I reverted this change in d7b7e2026b0a8b575df9ee7c4042ecff450f6549</div><div><br></div><div>Please run tests before committing.</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Mar 12, 2021 at 2:32 PM Nico Weber <<a href="mailto:thakis@chromium.org">thakis@chromium.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir="ltr">Hi,<div><br></div><div>this test fails: <a href="http://45.33.8.238/linux/41592/step_7.txt" target="_blank">http://45.33.8.238/linux/41592/step_7.txt</a></div><div><br></div><div>Please take a look, and please revert for now if it takes a while to fix.</div><div><br></div><div>Thanks,</div><div>Nico</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Mar 12, 2021 at 2:21 PM David Green via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org" target="_blank">cfe-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: David Green<br>
Date: 2021-03-12T19:21:21Z<br>
New Revision: 5ae949a9276542b46f41374fbe7aee01e480d9d6<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/5ae949a9276542b46f41374fbe7aee01e480d9d6" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/5ae949a9276542b46f41374fbe7aee01e480d9d6</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/5ae949a9276542b46f41374fbe7aee01e480d9d6.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/5ae949a9276542b46f41374fbe7aee01e480d9d6.diff</a><br>
<br>
LOG: [Clang][ARM] Reenable arm_acle.c test.<br>
<br>
This test was apparently disabled in 6fcd4e080f09c9765d6, without any<br>
sign of how it was going to be reenabled. This patch rewrites the test<br>
to use update_cc_test_checks, with midend optimizations other that<br>
mem2reg disabled.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
clang/test/CodeGen/arm_acle.c<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c<br>
index 9f0ad22bda4f..7e85c767c301 100644<br>
--- a/clang/test/CodeGen/arm_acle.c<br>
+++ b/clang/test/CodeGen/arm_acle.c<br>
@@ -1,125 +1,229 @@<br>
-// RUN: %clang_cc1 -ffreestanding -triple armv8-eabi -target-cpu cortex-a57 -O2 -fno-experimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch32 -check-prefix=ARM-LEGACY -check-prefix=AArch32-LEGACY<br>
-// RUN: %clang_cc1 -ffreestanding -triple armv8-eabi -target-cpu cortex-a57 -O2 -fexperimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch32 -check-prefix=ARM-NEWPM -check-prefix=AArch32-NEWPM<br>
-// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +neon -target-feature +crc -target-feature +crypto -O2 -fno-experimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch64 -check-prefix=ARM-LEGACY -check-prefix=AArch64-LEGACY<br>
-// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +neon -target-feature +crc -target-feature +crypto -O2 -fexperimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch64 -check-prefix=ARM-NEWPM -check-prefix=AArch64-NEWPM<br>
-// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +v8.3a -O2 -fexperimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=AArch64-v8_3<br>
-// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +v8.4a -O2 -fexperimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=AArch64-v8_3<br>
-// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +v8.5a -O2 -fexperimental-new-pass-manager -S -emit-llvm -o - %s | FileCheck %s -check-prefix=AArch64-v8_3<br>
-<br>
-// REQUIRES: rewrite<br>
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py<br>
+// RUN: %clang_cc1 -ffreestanding -triple armv8-eabi -target-cpu cortex-a57 -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch32<br>
+// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +neon -target-feature +crc -target-feature +crypto -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64<br>
+// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +v8.3a -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483<br>
+// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +v8.5a -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483<br>
<br>
#include <arm_acle.h><br>
<br>
/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */<br>
/* 8.3 Memory Barriers */<br>
-// ARM-LABEL: test_dmb<br>
-// AArch32: call void @llvm.arm.dmb(i32 1)<br>
-// AArch64: call void @llvm.aarch64.dmb(i32 1)<br>
+<br>
+// AArch32-LABEL: @test_dmb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.dmb(i32 1)<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_dmb(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.dmb(i32 1)<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_dmb(void) {<br>
__dmb(1);<br>
}<br>
<br>
-// ARM-LABEL: test_dsb<br>
-// AArch32: call void @llvm.arm.dsb(i32 2)<br>
-// AArch64: call void @llvm.aarch64.dsb(i32 2)<br>
+// AArch32-LABEL: @test_dsb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.dsb(i32 2)<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_dsb(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.dsb(i32 2)<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_dsb(void) {<br>
__dsb(2);<br>
}<br>
<br>
-// ARM-LABEL: test_isb<br>
-// AArch32: call void @llvm.arm.isb(i32 3)<br>
-// AArch64: call void @llvm.aarch64.isb(i32 3)<br>
+// AArch32-LABEL: @test_isb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.isb(i32 3)<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_isb(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.isb(i32 3)<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_isb(void) {<br>
__isb(3);<br>
}<br>
<br>
/* 8.4 Hints */<br>
-// ARM-LABEL: test_yield<br>
-// AArch32: call void @llvm.arm.hint(i32 1)<br>
-// AArch64: call void @llvm.aarch64.hint(i32 1)<br>
+// AArch32-LABEL: @test_yield(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.hint(i32 1) [[ATTR1:#.*]]<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_yield(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.hint(i32 1) [[ATTR3:#.*]]<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_yield(void) {<br>
__yield();<br>
}<br>
<br>
-// ARM-LABEL: test_wfe<br>
-// AArch32: call void @llvm.arm.hint(i32 2)<br>
-// AArch64: call void @llvm.aarch64.hint(i32 2)<br>
+// AArch32-LABEL: @test_wfe(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.hint(i32 2) [[ATTR1]]<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wfe(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.hint(i32 2) [[ATTR3]]<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wfe(void) {<br>
__wfe();<br>
}<br>
<br>
-// ARM-LABEL: test_wfi<br>
-// AArch32: call void @llvm.arm.hint(i32 3)<br>
-// AArch64: call void @llvm.aarch64.hint(i32 3)<br>
+// AArch32-LABEL: @test_wfi(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.hint(i32 3) [[ATTR1]]<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wfi(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.hint(i32 3) [[ATTR3]]<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wfi(void) {<br>
__wfi();<br>
}<br>
<br>
-// ARM-LABEL: test_sev<br>
-// AArch32: call void @llvm.arm.hint(i32 4)<br>
-// AArch64: call void @llvm.aarch64.hint(i32 4)<br>
+// AArch32-LABEL: @test_sev(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.hint(i32 4) [[ATTR1]]<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_sev(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.hint(i32 4) [[ATTR3]]<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_sev(void) {<br>
__sev();<br>
}<br>
<br>
-// ARM-LABEL: test_sevl<br>
-// AArch32: call void @llvm.arm.hint(i32 5)<br>
-// AArch64: call void @llvm.aarch64.hint(i32 5)<br>
+// AArch32-LABEL: @test_sevl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.hint(i32 5) [[ATTR1]]<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_sevl(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.hint(i32 5) [[ATTR3]]<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_sevl(void) {<br>
__sevl();<br>
}<br>
<br>
#if __ARM_32BIT_STATE<br>
-// AArch32-LABEL: test_dbg<br>
-// AArch32: call void @llvm.arm.dbg(i32 0)<br>
+// AArch32-LABEL: @test_dbg(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.dbg(i32 0)<br>
+// AArch32-NEXT: ret void<br>
+//<br>
void test_dbg(void) {<br>
__dbg(0);<br>
}<br>
#endif<br>
<br>
/* 8.5 Swap */<br>
-// ARM-LABEL: test_swp<br>
-// AArch32: call i32 @llvm.arm.ldrex<br>
-// AArch32: call i32 @llvm.arm.strex<br>
-// AArch64: call i64 @llvm.aarch64.ldxr<br>
-// AArch64: call i32 @llvm.aarch64.stxr<br>
+// AArch32-LABEL: @test_swp(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to i32*<br>
+// AArch32-NEXT: br label [[DO_BODY_I:%.*]]<br>
+// AArch32: do.body.i:<br>
+// AArch32-NEXT: [[LDREX_I:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[STREX_I:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[X:%.*]], i32* [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STREX_I]], 0<br>
+// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], [[LOOP3:!llvm.loop !.*]]<br>
+// AArch32: __swp.exit:<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_swp(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to i32*<br>
+// AArch64-NEXT: br label [[DO_BODY_I:%.*]]<br>
+// AArch64: do.body.i:<br>
+// AArch64-NEXT: [[LDXR_I:%.*]] = call i64 @llvm.aarch64.ldxr.p0i32(i32* [[TMP0]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[LDXR_I]] to i32<br>
+// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[X:%.*]] to i64<br>
+// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0i32(i64 [[TMP2]], i32* [[TMP0]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STXR_I]], 0<br>
+// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], [[LOOP6:!llvm.loop !.*]]<br>
+// AArch64: __swp.exit:<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_swp(uint32_t x, volatile void *p) {<br>
__swp(x, p);<br>
}<br>
<br>
/* 8.6 Memory prefetch intrinsics */<br>
/* 8.6.1 Data prefetch */<br>
-// ARM-LABEL: test_pld<br>
-// ARM: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 1)<br>
+// ARM-LABEL: @test_pld(<br>
+// ARM-NEXT: entry:<br>
+// ARM-NEXT: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 1)<br>
+// ARM-NEXT: ret void<br>
+//<br>
void test_pld() {<br>
__pld(0);<br>
}<br>
<br>
-// ARM-LABEL: test_pldx<br>
-// AArch32: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 3, i32 1)<br>
-// AArch64: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 1, i32 1)<br>
+// AArch32-LABEL: @test_pldx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 3, i32 1)<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_pldx(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.prefetch.p0i8(i8* null, i32 1, i32 1, i32 1)<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_pldx() {<br>
__pldx(1, 2, 0, 0);<br>
}<br>
<br>
/* 8.6.2 Instruction prefetch */<br>
-// ARM-LABEL: test_pli<br>
-// ARM: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0)<br>
+// ARM-LABEL: @test_pli(<br>
+// ARM-NEXT: entry:<br>
+// ARM-NEXT: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0)<br>
+// ARM-NEXT: ret void<br>
+//<br>
void test_pli() {<br>
__pli(0);<br>
}<br>
<br>
-// ARM-LABEL: test_plix<br>
-// AArch32: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0)<br>
-// AArch64: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 1, i32 0)<br>
+// AArch32-LABEL: @test_plix(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0)<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_plix(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.prefetch.p0i8(i8* null, i32 0, i32 1, i32 0)<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_plix() {<br>
__plix(2, 0, 0);<br>
}<br>
<br>
/* 8.7 NOP */<br>
-// ARM-LABEL: test_nop<br>
-// AArch32: call void @llvm.arm.hint(i32 0)<br>
-// AArch64: call void @llvm.aarch64.hint(i32 0)<br>
+// AArch32-LABEL: @test_nop(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.arm.hint(i32 0) [[ATTR1]]<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_nop(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.aarch64.hint(i32 0) [[ATTR3]]<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_nop(void) {<br>
__nop();<br>
}<br>
@@ -127,174 +231,465 @@ void test_nop(void) {<br>
/* 9 DATA-PROCESSING INTRINSICS */<br>
<br>
/* 9.2 Miscellaneous data-processing intrinsics */<br>
-// ARM-LABEL: test_ror<br>
-// ARM-LEGACY: lshr<br>
-// ARM-LEGACY: sub<br>
-// ARM-LEGACY: shl<br>
-// ARM-LEGACY: or<br>
-// ARM-NEWPM: call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %y)<br>
+// ARM-LABEL: @test_ror(<br>
+// ARM-NEXT: entry:<br>
+// ARM-NEXT: [[REM_I:%.*]] = urem i32 [[Y:%.*]], 32<br>
+// ARM-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[REM_I]], 0<br>
+// ARM-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]<br>
+// ARM: if.then.i:<br>
+// ARM-NEXT: br label [[__ROR_EXIT:%.*]]<br>
+// ARM: if.end.i:<br>
+// ARM-NEXT: [[SHR_I:%.*]] = lshr i32 [[X:%.*]], [[REM_I]]<br>
+// ARM-NEXT: [[SUB_I:%.*]] = sub i32 32, [[REM_I]]<br>
+// ARM-NEXT: [[SHL_I:%.*]] = shl i32 [[X]], [[SUB_I]]<br>
+// ARM-NEXT: [[OR_I:%.*]] = or i32 [[SHR_I]], [[SHL_I]]<br>
+// ARM-NEXT: br label [[__ROR_EXIT]]<br>
+// ARM: __ror.exit:<br>
+// ARM-NEXT: [[RETVAL_I_0:%.*]] = phi i32 [ [[X]], [[IF_THEN_I]] ], [ [[OR_I]], [[IF_END_I]] ]<br>
+// ARM-NEXT: ret i32 [[RETVAL_I_0]]<br>
+//<br>
uint32_t test_ror(uint32_t x, uint32_t y) {<br>
return __ror(x, y);<br>
}<br>
<br>
-// ARM-LABEL: test_rorl<br>
-// ARM-LEGACY: lshr<br>
-// ARM-LEGACY: sub<br>
-// ARM-LEGACY: shl<br>
-// ARM-LEGACY: or<br>
-// AArch32-NEWPM: call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %y)<br>
+// AArch32-LABEL: @test_rorl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[REM_I_I:%.*]] = urem i32 [[Y:%.*]], 32<br>
+// AArch32-NEXT: [[CMP_I_I:%.*]] = icmp eq i32 [[REM_I_I]], 0<br>
+// AArch32-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[IF_END_I_I:%.*]]<br>
+// AArch32: if.then.i.i:<br>
+// AArch32-NEXT: br label [[__RORL_EXIT:%.*]]<br>
+// AArch32: if.end.i.i:<br>
+// AArch32-NEXT: [[SHR_I_I:%.*]] = lshr i32 [[X:%.*]], [[REM_I_I]]<br>
+// AArch32-NEXT: [[SUB_I_I:%.*]] = sub i32 32, [[REM_I_I]]<br>
+// AArch32-NEXT: [[SHL_I_I:%.*]] = shl i32 [[X]], [[SUB_I_I]]<br>
+// AArch32-NEXT: [[OR_I_I:%.*]] = or i32 [[SHR_I_I]], [[SHL_I_I]]<br>
+// AArch32-NEXT: br label [[__RORL_EXIT]]<br>
+// AArch32: __rorl.exit:<br>
+// AArch32-NEXT: [[RETVAL_I_I_0:%.*]] = phi i32 [ [[X]], [[IF_THEN_I_I]] ], [ [[OR_I_I]], [[IF_END_I_I]] ]<br>
+// AArch32-NEXT: ret i32 [[RETVAL_I_I_0]]<br>
+//<br>
+// AArch64-LABEL: @test_rorl(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[REM_I_I:%.*]] = urem i32 [[Y:%.*]], 64<br>
+// AArch64-NEXT: [[CMP_I_I:%.*]] = icmp eq i32 [[REM_I_I]], 0<br>
+// AArch64-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[IF_END_I_I:%.*]]<br>
+// AArch64: if.then.i.i:<br>
+// AArch64-NEXT: br label [[__RORL_EXIT:%.*]]<br>
+// AArch64: if.end.i.i:<br>
+// AArch64-NEXT: [[SH_PROM_I_I:%.*]] = zext i32 [[REM_I_I]] to i64<br>
+// AArch64-NEXT: [[SHR_I_I:%.*]] = lshr i64 [[X:%.*]], [[SH_PROM_I_I]]<br>
+// AArch64-NEXT: [[SUB_I_I:%.*]] = sub i32 64, [[REM_I_I]]<br>
+// AArch64-NEXT: [[SH_PROM1_I_I:%.*]] = zext i32 [[SUB_I_I]] to i64<br>
+// AArch64-NEXT: [[SHL_I_I:%.*]] = shl i64 [[X]], [[SH_PROM1_I_I]]<br>
+// AArch64-NEXT: [[OR_I_I:%.*]] = or i64 [[SHR_I_I]], [[SHL_I_I]]<br>
+// AArch64-NEXT: br label [[__RORL_EXIT]]<br>
+// AArch64: __rorl.exit:<br>
+// AArch64-NEXT: [[RETVAL_I_I_0:%.*]] = phi i64 [ [[X]], [[IF_THEN_I_I]] ], [ [[OR_I_I]], [[IF_END_I_I]] ]<br>
+// AArch64-NEXT: ret i64 [[RETVAL_I_I_0]]<br>
+//<br>
unsigned long test_rorl(unsigned long x, uint32_t y) {<br>
return __rorl(x, y);<br>
}<br>
<br>
-// ARM-LABEL: test_rorll<br>
-// ARM: lshr<br>
-// ARM: sub<br>
-// ARM: shl<br>
-// ARM: or<br>
+// ARM-LABEL: @test_rorll(<br>
+// ARM-NEXT: entry:<br>
+// ARM-NEXT: [[REM_I:%.*]] = urem i32 [[Y:%.*]], 64<br>
+// ARM-NEXT: [[CMP_I:%.*]] = icmp eq i32 [[REM_I]], 0<br>
+// ARM-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[IF_END_I:%.*]]<br>
+// ARM: if.then.i:<br>
+// ARM-NEXT: br label [[__RORLL_EXIT:%.*]]<br>
+// ARM: if.end.i:<br>
+// ARM-NEXT: [[SH_PROM_I:%.*]] = zext i32 [[REM_I]] to i64<br>
+// ARM-NEXT: [[SHR_I:%.*]] = lshr i64 [[X:%.*]], [[SH_PROM_I]]<br>
+// ARM-NEXT: [[SUB_I:%.*]] = sub i32 64, [[REM_I]]<br>
+// ARM-NEXT: [[SH_PROM1_I:%.*]] = zext i32 [[SUB_I]] to i64<br>
+// ARM-NEXT: [[SHL_I:%.*]] = shl i64 [[X]], [[SH_PROM1_I]]<br>
+// ARM-NEXT: [[OR_I:%.*]] = or i64 [[SHR_I]], [[SHL_I]]<br>
+// ARM-NEXT: br label [[__RORLL_EXIT]]<br>
+// ARM: __rorll.exit:<br>
+// ARM-NEXT: [[RETVAL_I_0:%.*]] = phi i64 [ [[X]], [[IF_THEN_I]] ], [ [[OR_I]], [[IF_END_I]] ]<br>
+// ARM-NEXT: ret i64 [[RETVAL_I_0]]<br>
+//<br>
uint64_t test_rorll(uint64_t x, uint32_t y) {<br>
return __rorll(x, y);<br>
}<br>
<br>
-// ARM-LABEL: test_clz<br>
-// ARM: call i32 @llvm.ctlz.i32(i32 %t, i1 false)<br>
+// AArch32-LABEL: @test_clz(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_clz(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_clz(uint32_t t) {<br>
return __clz(t);<br>
}<br>
<br>
-// ARM-LABEL: test_clzl<br>
-// AArch32: call i32 @llvm.ctlz.i32(i32 %t, i1 false)<br>
-// AArch64: call i64 @llvm.ctlz.i64(i64 %t, i1 false)<br>
+// AArch32-LABEL: @test_clzl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.ctlz.i32(i32 [[T:%.*]], i1 false) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_clzl(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false) [[ATTR3]]<br>
+// AArch64-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32<br>
+// AArch64-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64<br>
+// AArch64-NEXT: ret i64 [[CONV_I]]<br>
+//<br>
long test_clzl(long t) {<br>
return __clzl(t);<br>
}<br>
<br>
-// ARM-LABEL: test_clzll<br>
-// ARM: call i64 @llvm.ctlz.i64(i64 %t, i1 false)<br>
+// AArch32-LABEL: @test_clzll(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false) [[ATTR1]]<br>
+// AArch32-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32<br>
+// AArch32-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64<br>
+// AArch32-NEXT: ret i64 [[CONV_I]]<br>
+//<br>
+// AArch64-LABEL: @test_clzll(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.ctlz.i64(i64 [[T:%.*]], i1 false) [[ATTR3]]<br>
+// AArch64-NEXT: [[CAST_I:%.*]] = trunc i64 [[TMP0]] to i32<br>
+// AArch64-NEXT: [[CONV_I:%.*]] = sext i32 [[CAST_I]] to i64<br>
+// AArch64-NEXT: ret i64 [[CONV_I]]<br>
+//<br>
uint64_t test_clzll(uint64_t t) {<br>
return __clzll(t);<br>
}<br>
<br>
-// ARM-LABEL: test_cls<br>
-// ARM: call i32 @llvm.arm.cls(i32 %t)<br>
+// AArch32-LABEL: @test_cls(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[CLS_I:%.*]] = call i32 @llvm.arm.cls(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[CLS_I]]<br>
+//<br>
+// AArch64-LABEL: @test_cls(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[CLS_I:%.*]] = call i32 @llvm.aarch64.cls(i32 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[CLS_I]]<br>
+//<br>
unsigned test_cls(uint32_t t) {<br>
return __cls(t);<br>
}<br>
<br>
-// ARM-LABEL: test_clsl<br>
-// AArch32: call i32 @llvm.arm.cls(i32 %t)<br>
-// AArch64: call i32 @llvm.arm.cls64(i64 %t)<br>
+// AArch32-LABEL: @test_clsl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[CLS_I:%.*]] = call i32 @llvm.arm.cls(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[CLS_I]]<br>
+//<br>
+// AArch64-LABEL: @test_clsl(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[CLS_I:%.*]] = call i32 @llvm.aarch64.cls64(i64 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[CLS_I]]<br>
+//<br>
unsigned test_clsl(unsigned long t) {<br>
return __clsl(t);<br>
}<br>
-// ARM-LABEL: test_clsll<br>
-// ARM: call i32 @llvm.arm.cls64(i64 %t)<br>
+<br>
+// AArch32-LABEL: @test_clsll(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[CLS_I:%.*]] = call i32 @llvm.arm.cls64(i64 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[CLS_I]]<br>
+//<br>
+// AArch64-LABEL: @test_clsll(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[CLS_I:%.*]] = call i32 @llvm.aarch64.cls64(i64 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[CLS_I]]<br>
+//<br>
unsigned test_clsll(uint64_t t) {<br>
return __clsll(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rev<br>
-// ARM: call i32 @llvm.bswap.i32(i32 %t)<br>
+// AArch32-LABEL: @test_rev(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_rev(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_rev(uint32_t t) {<br>
return __rev(t);<br>
}<br>
<br>
-// ARM-LABEL: test_revl<br>
-// AArch32: call i32 @llvm.bswap.i32(i32 %t)<br>
-// AArch64: call i64 @llvm.bswap.i64(i64 %t)<br>
+// AArch32-LABEL: @test_revl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_revl(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i64 [[TMP0]]<br>
+//<br>
long test_revl(long t) {<br>
return __revl(t);<br>
}<br>
<br>
-// ARM-LABEL: test_revll<br>
-// ARM: call i64 @llvm.bswap.i64(i64 %t)<br>
+// AArch32-LABEL: @test_revll(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i64 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_revll(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.bswap.i64(i64 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i64 [[TMP0]]<br>
+//<br>
uint64_t test_revll(uint64_t t) {<br>
return __revll(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rev16<br>
-// ARM: llvm.bswap<br>
-// ARM-LEGACY: lshr {{.*}}, 16<br>
-// ARM-LEGACY: shl {{.*}}, 16<br>
-// ARM-LEGACY: or<br>
-// ARM-NEWPM: call i32 @llvm.fshl.i32(i32 %0, i32 %0, i32 16)<br>
+// AArch32-LABEL: @test_rev16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[REM_I_I:%.*]] = urem i32 16, 32<br>
+// AArch32-NEXT: [[CMP_I_I:%.*]] = icmp eq i32 [[REM_I_I]], 0<br>
+// AArch32-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[IF_END_I_I:%.*]]<br>
+// AArch32: if.then.i.i:<br>
+// AArch32-NEXT: br label [[__REV16_EXIT:%.*]]<br>
+// AArch32: if.end.i.i:<br>
+// AArch32-NEXT: [[SHR_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I]]<br>
+// AArch32-NEXT: [[SUB_I_I:%.*]] = sub i32 32, [[REM_I_I]]<br>
+// AArch32-NEXT: [[SHL_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I]]<br>
+// AArch32-NEXT: [[OR_I_I:%.*]] = or i32 [[SHR_I_I]], [[SHL_I_I]]<br>
+// AArch32-NEXT: br label [[__REV16_EXIT]]<br>
+// AArch32: __rev16.exit:<br>
+// AArch32-NEXT: [[RETVAL_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I]] ], [ [[OR_I_I]], [[IF_END_I_I]] ]<br>
+// AArch32-NEXT: ret i32 [[RETVAL_I_I_0]]<br>
+//<br>
+// AArch64-LABEL: @test_rev16(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[REM_I_I:%.*]] = urem i32 16, 32<br>
+// AArch64-NEXT: [[CMP_I_I:%.*]] = icmp eq i32 [[REM_I_I]], 0<br>
+// AArch64-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[IF_END_I_I:%.*]]<br>
+// AArch64: if.then.i.i:<br>
+// AArch64-NEXT: br label [[__REV16_EXIT:%.*]]<br>
+// AArch64: if.end.i.i:<br>
+// AArch64-NEXT: [[SHR_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I]]<br>
+// AArch64-NEXT: [[SUB_I_I:%.*]] = sub i32 32, [[REM_I_I]]<br>
+// AArch64-NEXT: [[SHL_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I]]<br>
+// AArch64-NEXT: [[OR_I_I:%.*]] = or i32 [[SHR_I_I]], [[SHL_I_I]]<br>
+// AArch64-NEXT: br label [[__REV16_EXIT]]<br>
+// AArch64: __rev16.exit:<br>
+// AArch64-NEXT: [[RETVAL_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I]] ], [ [[OR_I_I]], [[IF_END_I_I]] ]<br>
+// AArch64-NEXT: ret i32 [[RETVAL_I_I_0]]<br>
+//<br>
uint32_t test_rev16(uint32_t t) {<br>
return __rev16(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rev16l<br>
-// AArch32: llvm.bswap<br>
-// AArch32-LEGACY: lshr {{.*}}, 16<br>
-// AArch32-LEGACY: shl {{.*}}, 16<br>
-// AArch32-LEGACY: or<br>
-// AArch32-NEWPM: call i32 @llvm.fshl.i32(i32 %0, i32 %0, i32 16)<br>
-// AArch64: [[T1:%.*]] = lshr i64 [[IN:%.*]], 32<br>
-// AArch64: [[T2:%.*]] = trunc i64 [[T1]] to i32<br>
-// AArch64: [[T3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T2]])<br>
-// AArch64-LEGACY: [[T4:%.*]] = lshr i32 [[T3]], 16<br>
-// AArch64-LEGACY: [[T5:%.*]] = shl i32 [[T3]], 16<br>
-// AArch64-LEGACY: [[T6:%.*]] = or i32 [[T5]], [[T4]]<br>
-// AArch64-NEWPM: [[T6:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[T3]], i32 [[T3]], i32 16)<br>
-// AArch64: [[T7:%.*]] = zext i32 [[T6]] to i64<br>
-// AArch64: [[T8:%.*]] = shl nuw i64 [[T7]], 32<br>
-// AArch64: [[T9:%.*]] = trunc i64 [[IN]] to i32<br>
-// AArch64: [[T10:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T9]])<br>
-// AArch64-LEGACY: [[T11:%.*]] = lshr i32 [[T10]], 16<br>
-// AArch64-LEGACY: [[T12:%.*]] = shl i32 [[T10]], 16<br>
-// AArch64-LEGACY: [[T13:%.*]] = or i32 [[T12]], [[T11]]<br>
-// AArch64-NEWPM: [[T13:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[T10]], i32 [[T10]], i32 16)<br>
-// AArch64: [[T14:%.*]] = zext i32 [[T13]] to i64<br>
-// AArch64: [[T15:%.*]] = or i64 [[T8]], [[T14]]<br>
+// AArch32-LABEL: @test_rev16l(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[REM_I_I_I:%.*]] = urem i32 16, 32<br>
+// AArch32-NEXT: [[CMP_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I]], 0<br>
+// AArch32-NEXT: br i1 [[CMP_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[IF_END_I_I_I:%.*]]<br>
+// AArch32: if.then.i.i.i:<br>
+// AArch32-NEXT: br label [[__REV16L_EXIT:%.*]]<br>
+// AArch32: if.end.i.i.i:<br>
+// AArch32-NEXT: [[SHR_I_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I_I]]<br>
+// AArch32-NEXT: [[SUB_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I]]<br>
+// AArch32-NEXT: [[SHL_I_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I_I]]<br>
+// AArch32-NEXT: [[OR_I_I_I:%.*]] = or i32 [[SHR_I_I_I]], [[SHL_I_I_I]]<br>
+// AArch32-NEXT: br label [[__REV16L_EXIT]]<br>
+// AArch32: __rev16l.exit:<br>
+// AArch32-NEXT: [[RETVAL_I_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I_I]] ], [ [[OR_I_I_I]], [[IF_END_I_I_I]] ]<br>
+// AArch32-NEXT: ret i32 [[RETVAL_I_I_I_0]]<br>
+//<br>
+// AArch64-LABEL: @test_rev16l(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[SHR_I_I:%.*]] = lshr i64 [[T:%.*]], 32<br>
+// AArch64-NEXT: [[CONV_I_I:%.*]] = trunc i64 [[SHR_I_I]] to i32<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I_I]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[REM_I_I_I_I:%.*]] = urem i32 16, 32<br>
+// AArch64-NEXT: [[CMP_I_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I_I]], 0<br>
+// AArch64-NEXT: br i1 [[CMP_I_I_I_I]], label [[IF_THEN_I_I_I_I:%.*]], label [[IF_END_I_I_I_I:%.*]]<br>
+// AArch64: if.then.i.i.i.i:<br>
+// AArch64-NEXT: br label [[__REV16_EXIT_I_I:%.*]]<br>
+// AArch64: if.end.i.i.i.i:<br>
+// AArch64-NEXT: [[SHR_I_I_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I_I_I]]<br>
+// AArch64-NEXT: [[SUB_I_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I_I]]<br>
+// AArch64-NEXT: [[SHL_I_I_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I_I_I]]<br>
+// AArch64-NEXT: [[OR_I_I_I_I:%.*]] = or i32 [[SHR_I_I_I_I]], [[SHL_I_I_I_I]]<br>
+// AArch64-NEXT: br label [[__REV16_EXIT_I_I]]<br>
+// AArch64: __rev16.exit.i.i:<br>
+// AArch64-NEXT: [[RETVAL_I_I_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I_I_I]] ], [ [[OR_I_I_I_I]], [[IF_END_I_I_I_I]] ]<br>
+// AArch64-NEXT: [[CONV1_I_I:%.*]] = zext i32 [[RETVAL_I_I_I_I_0]] to i64<br>
+// AArch64-NEXT: [[SHL_I_I:%.*]] = shl i64 [[CONV1_I_I]], 32<br>
+// AArch64-NEXT: [[CONV2_I_I:%.*]] = trunc i64 [[T]] to i32<br>
+// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV2_I_I]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[REM_I_I10_I_I:%.*]] = urem i32 16, 32<br>
+// AArch64-NEXT: [[CMP_I_I11_I_I:%.*]] = icmp eq i32 [[REM_I_I10_I_I]], 0<br>
+// AArch64-NEXT: br i1 [[CMP_I_I11_I_I]], label [[IF_THEN_I_I12_I_I:%.*]], label [[IF_END_I_I17_I_I:%.*]]<br>
+// AArch64: if.then.i.i12.i.i:<br>
+// AArch64-NEXT: br label [[__REV16L_EXIT:%.*]]<br>
+// AArch64: if.end.i.i17.i.i:<br>
+// AArch64-NEXT: [[SHR_I_I13_I_I:%.*]] = lshr i32 [[TMP1]], [[REM_I_I10_I_I]]<br>
+// AArch64-NEXT: [[SUB_I_I14_I_I:%.*]] = sub i32 32, [[REM_I_I10_I_I]]<br>
+// AArch64-NEXT: [[SHL_I_I15_I_I:%.*]] = shl i32 [[TMP1]], [[SUB_I_I14_I_I]]<br>
+// AArch64-NEXT: [[OR_I_I16_I_I:%.*]] = or i32 [[SHR_I_I13_I_I]], [[SHL_I_I15_I_I]]<br>
+// AArch64-NEXT: br label [[__REV16L_EXIT]]<br>
+// AArch64: __rev16l.exit:<br>
+// AArch64-NEXT: [[RETVAL_I_I5_I_I_0:%.*]] = phi i32 [ [[TMP1]], [[IF_THEN_I_I12_I_I]] ], [ [[OR_I_I16_I_I]], [[IF_END_I_I17_I_I]] ]<br>
+// AArch64-NEXT: [[CONV4_I_I:%.*]] = zext i32 [[RETVAL_I_I5_I_I_0]] to i64<br>
+// AArch64-NEXT: [[OR_I_I:%.*]] = or i64 [[SHL_I_I]], [[CONV4_I_I]]<br>
+// AArch64-NEXT: ret i64 [[OR_I_I]]<br>
+//<br>
long test_rev16l(long t) {<br>
return __rev16l(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rev16ll<br>
-// ARM: [[T1:%.*]] = lshr i64 [[IN:%.*]], 32<br>
-// ARM: [[T2:%.*]] = trunc i64 [[T1]] to i32<br>
-// ARM: [[T3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T2]])<br>
-// ARM-LEGACY: [[T4:%.*]] = lshr i32 [[T3]], 16<br>
-// ARM-LEGACY: [[T5:%.*]] = shl i32 [[T3]], 16<br>
-// ARM-LEGACY: [[T6:%.*]] = or i32 [[T5]], [[T4]]<br>
-// ARM-NEWPM: [[T6:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[T3]], i32 [[T3]], i32 16)<br>
-// ARM: [[T7:%.*]] = zext i32 [[T6]] to i64<br>
-// ARM: [[T8:%.*]] = shl nuw i64 [[T7]], 32<br>
-// ARM: [[T9:%.*]] = trunc i64 [[IN]] to i32<br>
-// ARM: [[T10:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[T9]])<br>
-// ARM-LEGACY: [[T11:%.*]] = lshr i32 [[T10]], 16<br>
-// ARM-LEGACY: [[T12:%.*]] = shl i32 [[T10]], 16<br>
-// ARM-LEGACY: [[T13:%.*]] = or i32 [[T12]], [[T11]]<br>
-// ARM-NEWPM: [[T13:%.*]] = tail call i32 @llvm.fshl.i32(i32 [[T10]], i32 [[T10]], i32 16)<br>
-// ARM: [[T14:%.*]] = zext i32 [[T13]] to i64<br>
-// ARM: [[T15:%.*]] = or i64 [[T8]], [[T14]]<br>
+// AArch32-LABEL: @test_rev16ll(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[SHR_I:%.*]] = lshr i64 [[T:%.*]], 32<br>
+// AArch32-NEXT: [[CONV_I:%.*]] = trunc i64 [[SHR_I]] to i32<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[REM_I_I_I:%.*]] = urem i32 16, 32<br>
+// AArch32-NEXT: [[CMP_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I]], 0<br>
+// AArch32-NEXT: br i1 [[CMP_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[IF_END_I_I_I:%.*]]<br>
+// AArch32: if.then.i.i.i:<br>
+// AArch32-NEXT: br label [[__REV16_EXIT_I:%.*]]<br>
+// AArch32: if.end.i.i.i:<br>
+// AArch32-NEXT: [[SHR_I_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I_I]]<br>
+// AArch32-NEXT: [[SUB_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I]]<br>
+// AArch32-NEXT: [[SHL_I_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I_I]]<br>
+// AArch32-NEXT: [[OR_I_I_I:%.*]] = or i32 [[SHR_I_I_I]], [[SHL_I_I_I]]<br>
+// AArch32-NEXT: br label [[__REV16_EXIT_I]]<br>
+// AArch32: __rev16.exit.i:<br>
+// AArch32-NEXT: [[RETVAL_I_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I_I]] ], [ [[OR_I_I_I]], [[IF_END_I_I_I]] ]<br>
+// AArch32-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I_I_0]] to i64<br>
+// AArch32-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32<br>
+// AArch32-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV2_I]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32<br>
+// AArch32-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0<br>
+// AArch32-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]]<br>
+// AArch32: if.then.i.i12.i:<br>
+// AArch32-NEXT: br label [[__REV16LL_EXIT:%.*]]<br>
+// AArch32: if.end.i.i17.i:<br>
+// AArch32-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP1]], [[REM_I_I10_I]]<br>
+// AArch32-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]<br>
+// AArch32-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP1]], [[SUB_I_I14_I]]<br>
+// AArch32-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]<br>
+// AArch32-NEXT: br label [[__REV16LL_EXIT]]<br>
+// AArch32: __rev16ll.exit:<br>
+// AArch32-NEXT: [[RETVAL_I_I5_I_0:%.*]] = phi i32 [ [[TMP1]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ]<br>
+// AArch32-NEXT: [[CONV4_I:%.*]] = zext i32 [[RETVAL_I_I5_I_0]] to i64<br>
+// AArch32-NEXT: [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV4_I]]<br>
+// AArch32-NEXT: ret i64 [[OR_I]]<br>
+//<br>
+// AArch64-LABEL: @test_rev16ll(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[SHR_I:%.*]] = lshr i64 [[T:%.*]], 32<br>
+// AArch64-NEXT: [[CONV_I:%.*]] = trunc i64 [[SHR_I]] to i32<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[REM_I_I_I:%.*]] = urem i32 16, 32<br>
+// AArch64-NEXT: [[CMP_I_I_I:%.*]] = icmp eq i32 [[REM_I_I_I]], 0<br>
+// AArch64-NEXT: br i1 [[CMP_I_I_I]], label [[IF_THEN_I_I_I:%.*]], label [[IF_END_I_I_I:%.*]]<br>
+// AArch64: if.then.i.i.i:<br>
+// AArch64-NEXT: br label [[__REV16_EXIT_I:%.*]]<br>
+// AArch64: if.end.i.i.i:<br>
+// AArch64-NEXT: [[SHR_I_I_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I_I]]<br>
+// AArch64-NEXT: [[SUB_I_I_I:%.*]] = sub i32 32, [[REM_I_I_I]]<br>
+// AArch64-NEXT: [[SHL_I_I_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I_I]]<br>
+// AArch64-NEXT: [[OR_I_I_I:%.*]] = or i32 [[SHR_I_I_I]], [[SHL_I_I_I]]<br>
+// AArch64-NEXT: br label [[__REV16_EXIT_I]]<br>
+// AArch64: __rev16.exit.i:<br>
+// AArch64-NEXT: [[RETVAL_I_I_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I_I]] ], [ [[OR_I_I_I]], [[IF_END_I_I_I]] ]<br>
+// AArch64-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I_I_0]] to i64<br>
+// AArch64-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32<br>
+// AArch64-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32<br>
+// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV2_I]]) [[ATTR3]]<br>
+// AArch64-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32<br>
+// AArch64-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0<br>
+// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]]<br>
+// AArch64: if.then.i.i12.i:<br>
+// AArch64-NEXT: br label [[__REV16LL_EXIT:%.*]]<br>
+// AArch64: if.end.i.i17.i:<br>
+// AArch64-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP1]], [[REM_I_I10_I]]<br>
+// AArch64-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]]<br>
+// AArch64-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP1]], [[SUB_I_I14_I]]<br>
+// AArch64-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]]<br>
+// AArch64-NEXT: br label [[__REV16LL_EXIT]]<br>
+// AArch64: __rev16ll.exit:<br>
+// AArch64-NEXT: [[RETVAL_I_I5_I_0:%.*]] = phi i32 [ [[TMP1]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ]<br>
+// AArch64-NEXT: [[CONV4_I:%.*]] = zext i32 [[RETVAL_I_I5_I_0]] to i64<br>
+// AArch64-NEXT: [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV4_I]]<br>
+// AArch64-NEXT: ret i64 [[OR_I]]<br>
+//<br>
uint64_t test_rev16ll(uint64_t t) {<br>
return __rev16ll(t);<br>
}<br>
<br>
-// ARM-LABEL: test_revsh<br>
-// ARM: call i16 @llvm.bswap.i16(i16 %t)<br>
+// AArch32-LABEL: @test_revsh(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i16 @llvm.bswap.i16(i16 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i16 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_revsh(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i16 @llvm.bswap.i16(i16 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i16 [[TMP0]]<br>
+//<br>
int16_t test_revsh(int16_t t) {<br>
return __revsh(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rbit<br>
-// AArch32: call i32 @llvm.bitreverse.i32<br>
-// AArch64: call i32 @llvm.bitreverse.i32<br>
+// AArch32-LABEL: @test_rbit(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[RBIT_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[RBIT_I]]<br>
+//<br>
+// AArch64-LABEL: @test_rbit(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[RBIT_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[RBIT_I]]<br>
+//<br>
uint32_t test_rbit(uint32_t t) {<br>
return __rbit(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rbitl<br>
-// AArch32: call i32 @llvm.bitreverse.i32<br>
-// AArch64: call i64 @llvm.bitreverse.i64<br>
+// AArch32-LABEL: @test_rbitl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[RBIT_I_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[T:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[RBIT_I_I]]<br>
+//<br>
+// AArch64-LABEL: @test_rbitl(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[RBIT_I_I:%.*]] = call i64 @llvm.bitreverse.i64(i64 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i64 [[RBIT_I_I]]<br>
+//<br>
long test_rbitl(long t) {<br>
return __rbitl(t);<br>
}<br>
<br>
-// ARM-LABEL: test_rbitll<br>
-// AArch32: call i32 @llvm.bitreverse.i32<br>
-// AArch32: call i32 @llvm.bitreverse.i32<br>
-// AArch64: call i64 @llvm.bitreverse.i64<br>
+// AArch32-LABEL: @test_rbitll(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[CONV_I:%.*]] = trunc i64 [[T:%.*]] to i32<br>
+// AArch32-NEXT: [[RBIT_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[CONV_I]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[CONV1_I:%.*]] = zext i32 [[RBIT_I]] to i64<br>
+// AArch32-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32<br>
+// AArch32-NEXT: [[SHR_I:%.*]] = lshr i64 [[T]], 32<br>
+// AArch32-NEXT: [[CONV2_I:%.*]] = trunc i64 [[SHR_I]] to i32<br>
+// AArch32-NEXT: [[RBIT3_I:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[CONV2_I]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[CONV4_I:%.*]] = zext i32 [[RBIT3_I]] to i64<br>
+// AArch32-NEXT: [[OR_I:%.*]] = or i64 [[SHL_I]], [[CONV4_I]]<br>
+// AArch32-NEXT: ret i64 [[OR_I]]<br>
+//<br>
+// AArch64-LABEL: @test_rbitll(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[RBIT_I:%.*]] = call i64 @llvm.bitreverse.i64(i64 [[T:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i64 [[RBIT_I]]<br>
+//<br>
uint64_t test_rbitll(uint64_t t) {<br>
return __rbitll(t);<br>
}<br>
@@ -302,14 +697,20 @@ uint64_t test_rbitll(uint64_t t) {<br>
/* 9.4 Saturating intrinsics */<br>
#ifdef __ARM_FEATURE_SAT<br>
/* 9.4.1 Width-specified saturation intrinsics */<br>
-// AArch32-LABEL: test_ssat<br>
-// AArch32: call i32 @llvm.arm.ssat(i32 %t, i32 1)<br>
+// AArch32-LABEL: @test_ssat(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssat(i32 [[T:%.*]], i32 1)<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_ssat(int32_t t) {<br>
return __ssat(t, 1);<br>
}<br>
<br>
-// AArch32-LABEL: test_usat<br>
-// AArch32: call i32 @llvm.arm.usat(i32 %t, i32 2)<br>
+// AArch32-LABEL: @test_usat(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usat(i32 [[T:%.*]], i32 2)<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_usat(int32_t t) {<br>
return __usat(t, 2);<br>
}<br>
@@ -317,23 +718,31 @@ uint32_t test_usat(int32_t t) {<br>
<br>
/* 9.4.2 Saturating addition and subtraction intrinsics */<br>
#ifdef __ARM_FEATURE_DSP<br>
-// AArch32-LABEL: test_qadd<br>
-// AArch32: call i32 @llvm.arm.qadd(i32 %a, i32 %b)<br>
+// AArch32-LABEL: @test_qadd(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_qadd(int32_t a, int32_t b) {<br>
return __qadd(a, b);<br>
}<br>
<br>
-// AArch32-LABEL: test_qsub<br>
-// AArch32: call i32 @llvm.arm.qsub(i32 %a, i32 %b)<br>
+// AArch32-LABEL: @test_qsub(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsub(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_qsub(int32_t a, int32_t b) {<br>
return __qsub(a, b);<br>
}<br>
<br>
extern int32_t f();<br>
-// AArch32-LABEL: test_qdbl<br>
-// AArch32: [[VAR:%[a-z0-9]+]] = {{.*}} call {{.*}} @f<br>
-// AArch32-NOT: call {{.*}} @f<br>
-// AArch32: call i32 @llvm.arm.qadd(i32 [[VAR]], i32 [[VAR]])<br>
+// AArch32-LABEL: @test_qdbl(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @f to i32 ()*)() [[ATTR7:#.*]]<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[CALL]], i32 [[CALL]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_qdbl() {<br>
return __qdbl(f());<br>
}<br>
@@ -343,33 +752,56 @@ int32_t test_qdbl() {<br>
* 9.3 16-bit multiplications<br>
*/<br>
#if __ARM_FEATURE_DSP<br>
-// AArch32-LABEL: test_smulbb<br>
-// AArch32: call i32 @llvm.arm.smulbb<br>
+// AArch32-LABEL: @test_smulbb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulbb(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smulbb(int32_t a, int32_t b) {<br>
return __smulbb(a, b);<br>
}<br>
-// AArch32-LABEL: test_smulbt<br>
-// AArch32: call i32 @llvm.arm.smulbt<br>
+<br>
+// AArch32-LABEL: @test_smulbt(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulbt(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smulbt(int32_t a, int32_t b) {<br>
return __smulbt(a, b);<br>
}<br>
-// AArch32-LABEL: test_smultb<br>
-// AArch32: call i32 @llvm.arm.smultb<br>
+<br>
+// AArch32-LABEL: @test_smultb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smultb(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smultb(int32_t a, int32_t b) {<br>
return __smultb(a, b);<br>
}<br>
-// AArch32-LABEL: test_smultt<br>
-// AArch32: call i32 @llvm.arm.smultt<br>
+<br>
+// AArch32-LABEL: @test_smultt(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smultt(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smultt(int32_t a, int32_t b) {<br>
return __smultt(a, b);<br>
}<br>
-// AArch32-LABEL: test_smulwb<br>
-// AArch32: call i32 @llvm.arm.smulwb<br>
+<br>
+// AArch32-LABEL: @test_smulwb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulwb(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smulwb(int32_t a, int32_t b) {<br>
return __smulwb(a, b);<br>
}<br>
-// AArch32-LABEL: test_smulwt<br>
-// AArch32: call i32 @llvm.arm.smulwt<br>
+<br>
+// AArch32-LABEL: @test_smulwt(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smulwt(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smulwt(int32_t a, int32_t b) {<br>
return __smulwt(a, b);<br>
}<br>
@@ -377,33 +809,56 @@ int32_t test_smulwt(int32_t a, int32_t b) {<br>
<br>
/* 9.4.3 Accumultating multiplications */<br>
#if __ARM_FEATURE_DSP<br>
-// AArch32-LABEL: test_smlabb<br>
-// AArch32: call i32 @llvm.arm.smlabb(i32 %a, i32 %b, i32 %c)<br>
+// AArch32-LABEL: @test_smlabb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlabb(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlabb(int32_t a, int32_t b, int32_t c) {<br>
return __smlabb(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlabt<br>
-// AArch32: call i32 @llvm.arm.smlabt(i32 %a, i32 %b, i32 %c)<br>
+<br>
+// AArch32-LABEL: @test_smlabt(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlabt(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlabt(int32_t a, int32_t b, int32_t c) {<br>
return __smlabt(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlatb<br>
-// AArch32: call i32 @llvm.arm.smlatb(i32 %a, i32 %b, i32 %c)<br>
+<br>
+// AArch32-LABEL: @test_smlatb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlatb(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlatb(int32_t a, int32_t b, int32_t c) {<br>
return __smlatb(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlatt<br>
-// AArch32: call i32 @llvm.arm.smlatt(i32 %a, i32 %b, i32 %c)<br>
+<br>
+// AArch32-LABEL: @test_smlatt(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlatt(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlatt(int32_t a, int32_t b, int32_t c) {<br>
return __smlatt(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlawb<br>
-// AArch32: call i32 @llvm.arm.smlawb(i32 %a, i32 %b, i32 %c)<br>
+<br>
+// AArch32-LABEL: @test_smlawb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlawb(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlawb(int32_t a, int32_t b, int32_t c) {<br>
return __smlawb(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlawt<br>
-// AArch32: call i32 @llvm.arm.smlawt(i32 %a, i32 %b, i32 %c)<br>
+<br>
+// AArch32-LABEL: @test_smlawt(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlawt(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlawt(int32_t a, int32_t b, int32_t c) {<br>
return __smlawt(a, b, c);<br>
}<br>
@@ -411,13 +866,20 @@ int32_t test_smlawt(int32_t a, int32_t b, int32_t c) {<br>
<br>
/* 9.5.4 Parallel 16-bit saturation */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_ssat16<br>
-// AArch32: call i32 @llvm.arm.ssat16<br>
+// AArch32-LABEL: @test_ssat16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssat16(i32 [[A:%.*]], i32 15)<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_ssat16(int16x2_t a) {<br>
return __ssat16(a, 15);<br>
}<br>
-// AArch32-LABEL: test_usat16<br>
-// AArch32: call i32 @llvm.arm.usat16<br>
+<br>
+// AArch32-LABEL: @test_usat16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usat16(i32 [[A:%.*]], i32 15)<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_usat16(int16x2_t a) {<br>
return __usat16(a, 15);<br>
}<br>
@@ -425,23 +887,38 @@ uint16x2_t test_usat16(int16x2_t a) {<br>
<br>
/* 9.5.5 Packing and unpacking */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_sxtab16<br>
-// AArch32: call i32 @llvm.arm.sxtab16<br>
+// AArch32-LABEL: @test_sxtab16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sxtab16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_sxtab16(int16x2_t a, int8x4_t b) {<br>
return __sxtab16(a, b);<br>
}<br>
-// AArch32-LABEL: test_sxtb16<br>
-// AArch32: call i32 @llvm.arm.sxtb16<br>
+<br>
+// AArch32-LABEL: @test_sxtb16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sxtb16(i32 [[A:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_sxtb16(int8x4_t a) {<br>
return __sxtb16(a);<br>
}<br>
-// AArch32-LABEL: test_uxtab16<br>
-// AArch32: call i32 @llvm.arm.uxtab16<br>
+<br>
+// AArch32-LABEL: @test_uxtab16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uxtab16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_uxtab16(int16x2_t a, int8x4_t b) {<br>
return __uxtab16(a, b);<br>
}<br>
-// AArch32-LABEL: test_uxtb16<br>
-// AArch32: call i32 @llvm.arm.uxtb16<br>
+<br>
+// AArch32-LABEL: @test_uxtb16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uxtb16(i32 [[A:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_uxtb16(int8x4_t a) {<br>
return __uxtb16(a);<br>
}<br>
@@ -449,8 +926,11 @@ int16x2_t test_uxtb16(int8x4_t a) {<br>
<br>
/* 9.5.6 Parallel selection */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_sel<br>
-// AArch32: call i32 @llvm.arm.sel<br>
+// AArch32-LABEL: @test_sel(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sel(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_sel(uint8x4_t a, uint8x4_t b) {<br>
return __sel(a, b);<br>
}<br>
@@ -458,63 +938,110 @@ uint8x4_t test_sel(uint8x4_t a, uint8x4_t b) {<br>
<br>
/* 9.5.7 Parallel 8-bit addition and subtraction */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_qadd8<br>
-// AArch32: call i32 @llvm.arm.qadd8<br>
+// AArch32-LABEL: @test_qadd8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_qadd8(int8x4_t a, int8x4_t b) {<br>
return __qadd8(a, b);<br>
}<br>
-// AArch32-LABEL: test_qsub8<br>
-// AArch32: call i32 @llvm.arm.qsub8<br>
+<br>
+// AArch32-LABEL: @test_qsub8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsub8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int8x4_t test_qsub8(int8x4_t a, int8x4_t b) {<br>
return __qsub8(a, b);<br>
}<br>
-// AArch32-LABEL: test_sadd8<br>
-// AArch32: call i32 @llvm.arm.sadd8<br>
+<br>
+// AArch32-LABEL: @test_sadd8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sadd8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int8x4_t test_sadd8(int8x4_t a, int8x4_t b) {<br>
return __sadd8(a, b);<br>
}<br>
-// AArch32-LABEL: test_shadd8<br>
-// AArch32: call i32 @llvm.arm.shadd8<br>
+<br>
+// AArch32-LABEL: @test_shadd8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shadd8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int8x4_t test_shadd8(int8x4_t a, int8x4_t b) {<br>
return __shadd8(a, b);<br>
}<br>
-// AArch32-LABEL: test_shsub8<br>
-// AArch32: call i32 @llvm.arm.shsub8<br>
+<br>
+// AArch32-LABEL: @test_shsub8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shsub8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int8x4_t test_shsub8(int8x4_t a, int8x4_t b) {<br>
return __shsub8(a, b);<br>
}<br>
-// AArch32-LABEL: test_ssub8<br>
-// AArch32: call i32 @llvm.arm.ssub8<br>
+<br>
+// AArch32-LABEL: @test_ssub8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssub8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int8x4_t test_ssub8(int8x4_t a, int8x4_t b) {<br>
return __ssub8(a, b);<br>
}<br>
-// AArch32-LABEL: test_uadd8<br>
-// AArch32: call i32 @llvm.arm.uadd8<br>
+<br>
+// AArch32-LABEL: @test_uadd8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uadd8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_uadd8(uint8x4_t a, uint8x4_t b) {<br>
return __uadd8(a, b);<br>
}<br>
-// AArch32-LABEL: test_uhadd8<br>
-// AArch32: call i32 @llvm.arm.uhadd8<br>
+<br>
+// AArch32-LABEL: @test_uhadd8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhadd8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_uhadd8(uint8x4_t a, uint8x4_t b) {<br>
return __uhadd8(a, b);<br>
}<br>
-// AArch32-LABEL: test_uhsub8<br>
-// AArch32: call i32 @llvm.arm.uhsub8<br>
+<br>
+// AArch32-LABEL: @test_uhsub8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhsub8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_uhsub8(uint8x4_t a, uint8x4_t b) {<br>
return __uhsub8(a, b);<br>
}<br>
-// AArch32-LABEL: test_uqadd8<br>
-// AArch32: call i32 @llvm.arm.uqadd8<br>
+<br>
+// AArch32-LABEL: @test_uqadd8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqadd8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_uqadd8(uint8x4_t a, uint8x4_t b) {<br>
return __uqadd8(a, b);<br>
}<br>
-// AArch32-LABEL: test_uqsub8<br>
-// AArch32: call i32 @llvm.arm.uqsub8<br>
+<br>
+// AArch32-LABEL: @test_uqsub8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqsub8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_uqsub8(uint8x4_t a, uint8x4_t b) {<br>
return __uqsub8(a, b);<br>
}<br>
-// AArch32-LABEL: test_usub8<br>
-// AArch32: call i32 @llvm.arm.usub8<br>
+<br>
+// AArch32-LABEL: @test_usub8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usub8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint8x4_t test_usub8(uint8x4_t a, uint8x4_t b) {<br>
return __usub8(a, b);<br>
}<br>
@@ -522,13 +1049,23 @@ uint8x4_t test_usub8(uint8x4_t a, uint8x4_t b) {<br>
<br>
/* 9.5.8 Sum of 8-bit absolute <br>
diff erences */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_usad8<br>
-// AArch32: call i32 @llvm.arm.usad8<br>
+// AArch32-LABEL: @test_usad8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usad8(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_usad8(uint8x4_t a, uint8x4_t b) {<br>
return __usad8(a, b);<br>
}<br>
-// AArch32-LABEL: test_usada8<br>
-// AArch32: call i32 @llvm.arm.usada8<br>
+<br>
+// AArch32-LABEL: @test_usada8(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32<br>
+// AArch32-NEXT: [[CONV1:%.*]] = zext i8 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[CONV2:%.*]] = zext i8 [[C:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usada8(i32 [[CONV]], i32 [[CONV1]], i32 [[CONV2]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_usada8(uint8_t a, uint8_t b, uint8_t c) {<br>
return __usada8(a, b, c);<br>
}<br>
@@ -536,123 +1073,218 @@ uint32_t test_usada8(uint8_t a, uint8_t b, uint8_t c) {<br>
<br>
/* 9.5.9 Parallel 16-bit addition and subtraction */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_qadd16<br>
-// AArch32: call i32 @llvm.arm.qadd16<br>
+// AArch32-LABEL: @test_qadd16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_qadd16(int16x2_t a, int16x2_t b) {<br>
return __qadd16(a, b);<br>
}<br>
-// AArch32-LABEL: test_qasx<br>
-// AArch32: call i32 @llvm.arm.qasx<br>
+<br>
+// AArch32-LABEL: @test_qasx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qasx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_qasx(int16x2_t a, int16x2_t b) {<br>
return __qasx(a, b);<br>
}<br>
-// AArch32-LABEL: test_qsax<br>
-// AArch32: call i32 @llvm.arm.qsax<br>
+<br>
+// AArch32-LABEL: @test_qsax(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsax(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_qsax(int16x2_t a, int16x2_t b) {<br>
return __qsax(a, b);<br>
}<br>
-// AArch32-LABEL: test_qsub16<br>
-// AArch32: call i32 @llvm.arm.qsub16<br>
+<br>
+// AArch32-LABEL: @test_qsub16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qsub16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_qsub16(int16x2_t a, int16x2_t b) {<br>
return __qsub16(a, b);<br>
}<br>
-// AArch32-LABEL: test_sadd16<br>
-// AArch32: call i32 @llvm.arm.sadd16<br>
+<br>
+// AArch32-LABEL: @test_sadd16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sadd16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_sadd16(int16x2_t a, int16x2_t b) {<br>
return __sadd16(a, b);<br>
}<br>
-// AArch32-LABEL: test_sasx<br>
-// AArch32: call i32 @llvm.arm.sasx<br>
+<br>
+// AArch32-LABEL: @test_sasx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.sasx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_sasx(int16x2_t a, int16x2_t b) {<br>
return __sasx(a, b);<br>
}<br>
-// AArch32-LABEL: test_shadd16<br>
-// AArch32: call i32 @llvm.arm.shadd16<br>
+<br>
+// AArch32-LABEL: @test_shadd16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shadd16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_shadd16(int16x2_t a, int16x2_t b) {<br>
return __shadd16(a, b);<br>
}<br>
-// AArch32-LABEL: test_shasx<br>
-// AArch32: call i32 @llvm.arm.shasx<br>
+<br>
+// AArch32-LABEL: @test_shasx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shasx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_shasx(int16x2_t a, int16x2_t b) {<br>
return __shasx(a, b);<br>
}<br>
-// AArch32-LABEL: test_shsax<br>
-// AArch32: call i32 @llvm.arm.shsax<br>
+<br>
+// AArch32-LABEL: @test_shsax(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shsax(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_shsax(int16x2_t a, int16x2_t b) {<br>
return __shsax(a, b);<br>
}<br>
-// AArch32-LABEL: test_shsub16<br>
-// AArch32: call i32 @llvm.arm.shsub16<br>
+<br>
+// AArch32-LABEL: @test_shsub16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.shsub16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_shsub16(int16x2_t a, int16x2_t b) {<br>
return __shsub16(a, b);<br>
}<br>
-// AArch32-LABEL: test_ssax<br>
-// AArch32: call i32 @llvm.arm.ssax<br>
+<br>
+// AArch32-LABEL: @test_ssax(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssax(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_ssax(int16x2_t a, int16x2_t b) {<br>
return __ssax(a, b);<br>
}<br>
-// AArch32-LABEL: test_ssub16<br>
-// AArch32: call i32 @llvm.arm.ssub16<br>
+<br>
+// AArch32-LABEL: @test_ssub16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.ssub16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int16x2_t test_ssub16(int16x2_t a, int16x2_t b) {<br>
return __ssub16(a, b);<br>
}<br>
-// AArch32-LABEL: test_uadd16<br>
-// AArch32: call i32 @llvm.arm.uadd16<br>
+<br>
+// AArch32-LABEL: @test_uadd16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uadd16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uadd16(uint16x2_t a, uint16x2_t b) {<br>
return __uadd16(a, b);<br>
}<br>
-// AArch32-LABEL: test_uasx<br>
-// AArch32: call i32 @llvm.arm.uasx<br>
+<br>
+// AArch32-LABEL: @test_uasx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uasx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uasx(uint16x2_t a, uint16x2_t b) {<br>
return __uasx(a, b);<br>
}<br>
-// AArch32-LABEL: test_uhadd16<br>
-// AArch32: call i32 @llvm.arm.uhadd16<br>
+<br>
+// AArch32-LABEL: @test_uhadd16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhadd16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uhadd16(uint16x2_t a, uint16x2_t b) {<br>
return __uhadd16(a, b);<br>
}<br>
-// AArch32-LABEL: test_uhasx<br>
-// AArch32: call i32 @llvm.arm.uhasx<br>
+<br>
+// AArch32-LABEL: @test_uhasx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhasx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uhasx(uint16x2_t a, uint16x2_t b) {<br>
return __uhasx(a, b);<br>
}<br>
-// AArch32-LABEL: test_uhsax<br>
-// AArch32: call i32 @llvm.arm.uhsax<br>
+<br>
+// AArch32-LABEL: @test_uhsax(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhsax(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uhsax(uint16x2_t a, uint16x2_t b) {<br>
return __uhsax(a, b);<br>
}<br>
-// AArch32-LABEL: test_uhsub16<br>
-// AArch32: call i32 @llvm.arm.uhsub16<br>
+<br>
+// AArch32-LABEL: @test_uhsub16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uhsub16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uhsub16(uint16x2_t a, uint16x2_t b) {<br>
return __uhsub16(a, b);<br>
}<br>
-// AArch32-LABEL: test_uqadd16<br>
-// AArch32: call i32 @llvm.arm.uqadd16<br>
+<br>
+// AArch32-LABEL: @test_uqadd16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqadd16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uqadd16(uint16x2_t a, uint16x2_t b) {<br>
return __uqadd16(a, b);<br>
}<br>
-// AArch32-LABEL: test_uqasx<br>
-// AArch32: call i32 @llvm.arm.uqasx<br>
+<br>
+// AArch32-LABEL: @test_uqasx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqasx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uqasx(uint16x2_t a, uint16x2_t b) {<br>
return __uqasx(a, b);<br>
}<br>
-// AArch32-LABEL: test_uqsax<br>
-// AArch32: call i32 @llvm.arm.uqsax<br>
+<br>
+// AArch32-LABEL: @test_uqsax(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqsax(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uqsax(uint16x2_t a, uint16x2_t b) {<br>
return __uqsax(a, b);<br>
}<br>
-// AArch32-LABEL: test_uqsub16<br>
-// AArch32: call i32 @llvm.arm.uqsub16<br>
+<br>
+// AArch32-LABEL: @test_uqsub16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.uqsub16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_uqsub16(uint16x2_t a, uint16x2_t b) {<br>
return __uqsub16(a, b);<br>
}<br>
-// AArch32-LABEL: test_usax<br>
-// AArch32: call i32 @llvm.arm.usax<br>
+<br>
+// AArch32-LABEL: @test_usax(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usax(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_usax(uint16x2_t a, uint16x2_t b) {<br>
return __usax(a, b);<br>
}<br>
-// AArch32-LABEL: test_usub16<br>
-// AArch32: call i32 @llvm.arm.usub16<br>
+<br>
+// AArch32-LABEL: @test_usub16(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.usub16(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint16x2_t test_usub16(uint16x2_t a, uint16x2_t b) {<br>
return __usub16(a, b);<br>
}<br>
@@ -660,131 +1292,256 @@ uint16x2_t test_usub16(uint16x2_t a, uint16x2_t b) {<br>
<br>
/* 9.5.10 Parallel 16-bit multiplications */<br>
#if __ARM_FEATURE_SIMD32<br>
-// AArch32-LABEL: test_smlad<br>
-// AArch32: call i32 @llvm.arm.smlad<br>
+// AArch32-LABEL: @test_smlad(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlad(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlad(int16x2_t a, int16x2_t b, int32_t c) {<br>
return __smlad(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smladx<br>
-// AArch32: call i32 @llvm.arm.smladx<br>
+<br>
+// AArch32-LABEL: @test_smladx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smladx(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smladx(int16x2_t a, int16x2_t b, int32_t c) {<br>
return __smladx(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlald<br>
-// AArch32: call i64 @llvm.arm.smlald<br>
+<br>
+// AArch32-LABEL: @test_smlald(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlald(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i64 [[TMP0]]<br>
+//<br>
int64_t test_smlald(int16x2_t a, int16x2_t b, int64_t c) {<br>
return __smlald(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlaldx<br>
-// AArch32: call i64 @llvm.arm.smlaldx<br>
+<br>
+// AArch32-LABEL: @test_smlaldx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlaldx(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i64 [[TMP0]]<br>
+//<br>
int64_t test_smlaldx(int16x2_t a, int16x2_t b, int64_t c) {<br>
return __smlaldx(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlsd<br>
-// AArch32: call i32 @llvm.arm.smlsd<br>
+<br>
+// AArch32-LABEL: @test_smlsd(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlsd(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlsd(int16x2_t a, int16x2_t b, int32_t c) {<br>
return __smlsd(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlsdx<br>
-// AArch32: call i32 @llvm.arm.smlsdx<br>
+<br>
+// AArch32-LABEL: @test_smlsdx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smlsdx(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smlsdx(int16x2_t a, int16x2_t b, int32_t c) {<br>
return __smlsdx(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlsld<br>
-// AArch32: call i64 @llvm.arm.smlsld<br>
+<br>
+// AArch32-LABEL: @test_smlsld(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlsld(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i64 [[TMP0]]<br>
+//<br>
int64_t test_smlsld(int16x2_t a, int16x2_t b, int64_t c) {<br>
return __smlsld(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smlsldx<br>
-// AArch32: call i64 @llvm.arm.smlsldx<br>
+<br>
+// AArch32-LABEL: @test_smlsldx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.arm.smlsldx(i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i64 [[TMP0]]<br>
+//<br>
int64_t test_smlsldx(int16x2_t a, int16x2_t b, int64_t c) {<br>
return __smlsldx(a, b, c);<br>
}<br>
-// AArch32-LABEL: test_smuad<br>
-// AArch32: call i32 @llvm.arm.smuad<br>
+<br>
+// AArch32-LABEL: @test_smuad(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smuad(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smuad(int16x2_t a, int16x2_t b) {<br>
return __smuad(a, b);<br>
}<br>
-// AArch32-LABEL: test_smuadx<br>
-// AArch32: call i32 @llvm.arm.smuadx<br>
+<br>
+// AArch32-LABEL: @test_smuadx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smuadx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smuadx(int16x2_t a, int16x2_t b) {<br>
return __smuadx(a, b);<br>
}<br>
-// AArch32-LABEL: test_smusd<br>
-// AArch32: call i32 @llvm.arm.smusd<br>
+<br>
+// AArch32-LABEL: @test_smusd(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smusd(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smusd(int16x2_t a, int16x2_t b) {<br>
return __smusd(a, b);<br>
}<br>
-// AArch32-LABEL: test_smusdx<br>
-// AArch32: call i32 @llvm.arm.smusdx<br>
+<br>
+// AArch32-LABEL: @test_smusdx(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.smusdx(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_smusdx(int16x2_t a, int16x2_t b) {<br>
return __smusdx(a, b);<br>
}<br>
#endif<br>
<br>
/* 9.7 CRC32 intrinsics */<br>
-// ARM-LABEL: test_crc32b<br>
-// AArch32: call i32 @llvm.arm.crc32b<br>
-// AArch64: call i32 @llvm.aarch64.crc32b<br>
+// AArch32-LABEL: @test_crc32b(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32b(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP1]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32b(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i32<br>
+// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32b(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP1]]<br>
+//<br>
uint32_t test_crc32b(uint32_t a, uint8_t b) {<br>
return __crc32b(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32h<br>
-// AArch32: call i32 @llvm.arm.crc32h<br>
-// AArch64: call i32 @llvm.aarch64.crc32h<br>
+// AArch32-LABEL: @test_crc32h(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32h(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP1]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32h(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i32<br>
+// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32h(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP1]]<br>
+//<br>
uint32_t test_crc32h(uint32_t a, uint16_t b) {<br>
return __crc32h(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32w<br>
-// AArch32: call i32 @llvm.arm.crc32w<br>
-// AArch64: call i32 @llvm.aarch64.crc32w<br>
+// AArch32-LABEL: @test_crc32w(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.crc32w(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32w(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32w(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_crc32w(uint32_t a, uint32_t b) {<br>
return __crc32w(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32d<br>
-// AArch32: call i32 @llvm.arm.crc32w<br>
-// AArch32: call i32 @llvm.arm.crc32w<br>
-// AArch64: call i32 @llvm.aarch64.crc32x<br>
+// AArch32-LABEL: @test_crc32d(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = trunc i64 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = lshr i64 [[B]], 32<br>
+// AArch32-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32<br>
+// AArch32-NEXT: [[TMP3:%.*]] = call i32 @llvm.arm.crc32w(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.crc32w(i32 [[TMP3]], i32 [[TMP2]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP4]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32d(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32x(i32 [[A:%.*]], i64 [[B:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_crc32d(uint32_t a, uint64_t b) {<br>
return __crc32d(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32cb<br>
-// AArch32: call i32 @llvm.arm.crc32cb<br>
-// AArch64: call i32 @llvm.aarch64.crc32cb<br>
+// AArch32-LABEL: @test_crc32cb(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32cb(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP1]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32cb(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = zext i8 [[B:%.*]] to i32<br>
+// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32cb(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP1]]<br>
+//<br>
uint32_t test_crc32cb(uint32_t a, uint8_t b) {<br>
return __crc32cb(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32ch<br>
-// AArch32: call i32 @llvm.arm.crc32ch<br>
-// AArch64: call i32 @llvm.aarch64.crc32ch<br>
+// AArch32-LABEL: @test_crc32ch(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.crc32ch(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP1]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32ch(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = zext i16 [[B:%.*]] to i32<br>
+// AArch64-NEXT: [[TMP1:%.*]] = call i32 @llvm.aarch64.crc32ch(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP1]]<br>
+//<br>
uint32_t test_crc32ch(uint32_t a, uint16_t b) {<br>
return __crc32ch(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32cw<br>
-// AArch32: call i32 @llvm.arm.crc32cw<br>
-// AArch64: call i32 @llvm.aarch64.crc32cw<br>
+// AArch32-LABEL: @test_crc32cw(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.crc32cw(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32cw(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32cw(i32 [[A:%.*]], i32 [[B:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_crc32cw(uint32_t a, uint32_t b) {<br>
return __crc32cw(a, b);<br>
}<br>
<br>
-// ARM-LABEL: test_crc32cd<br>
-// AArch32: call i32 @llvm.arm.crc32cw<br>
-// AArch32: call i32 @llvm.arm.crc32cw<br>
-// AArch64: call i32 @llvm.aarch64.crc32cx<br>
+// AArch32-LABEL: @test_crc32cd(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = trunc i64 [[B:%.*]] to i32<br>
+// AArch32-NEXT: [[TMP1:%.*]] = lshr i64 [[B]], 32<br>
+// AArch32-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32<br>
+// AArch32-NEXT: [[TMP3:%.*]] = call i32 @llvm.arm.crc32cw(i32 [[A:%.*]], i32 [[TMP0]]) [[ATTR1]]<br>
+// AArch32-NEXT: [[TMP4:%.*]] = call i32 @llvm.arm.crc32cw(i32 [[TMP3]], i32 [[TMP2]]) [[ATTR1]]<br>
+// AArch32-NEXT: ret i32 [[TMP4]]<br>
+//<br>
+// AArch64-LABEL: @test_crc32cd(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.crc32cx(i32 [[A:%.*]], i64 [[B:%.*]]) [[ATTR3]]<br>
+// AArch64-NEXT: ret i32 [[TMP0]]<br>
+//<br>
uint32_t test_crc32cd(uint32_t a, uint64_t b) {<br>
return __crc32cd(a, b);<br>
}<br>
<br>
/* 10.1 Special register intrinsics */<br>
-// ARM-LABEL: test_rsr<br>
-// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])<br>
-// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]])<br>
+// AArch32-LABEL: @test_rsr(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata !5)<br>
+// AArch32-NEXT: ret i32 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_rsr(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !8)<br>
+// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32<br>
+// AArch64-NEXT: ret i32 [[TMP1]]<br>
+//<br>
uint32_t test_rsr() {<br>
#ifdef __ARM_32BIT_STATE<br>
return __arm_rsr("cp1:2:c3:c4:5");<br>
@@ -793,9 +1550,16 @@ uint32_t test_rsr() {<br>
#endif<br>
}<br>
<br>
-// ARM-LABEL: test_rsr64<br>
-// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])<br>
-// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]])<br>
+// AArch32-LABEL: @test_rsr64(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !6)<br>
+// AArch32-NEXT: ret i64 [[TMP0]]<br>
+//<br>
+// AArch64-LABEL: @test_rsr64(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !8)<br>
+// AArch64-NEXT: ret i64 [[TMP0]]<br>
+//<br>
uint64_t test_rsr64() {<br>
#ifdef __ARM_32BIT_STATE<br>
return __arm_rsr64("cp1:2:c3");<br>
@@ -804,16 +1568,33 @@ uint64_t test_rsr64() {<br>
#endif<br>
}<br>
<br>
-// ARM-LABEL: test_rsrp<br>
-// AArch64: call i64 @llvm.read_register.i64(metadata ![[M1:[0-9]]])<br>
-// AArch32: call i32 @llvm.read_register.i32(metadata ![[M4:[0-9]]])<br>
+// AArch32-LABEL: @test_rsrp(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata !7)<br>
+// AArch32-NEXT: [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to i8*<br>
+// AArch32-NEXT: ret i8* [[TMP1]]<br>
+//<br>
+// AArch64-LABEL: @test_rsrp(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !9)<br>
+// AArch64-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to i8*<br>
+// AArch64-NEXT: ret i8* [[TMP1]]<br>
+//<br>
void *test_rsrp() {<br>
return __arm_rsrp("sysreg");<br>
}<br>
<br>
-// ARM-LABEL: test_wsr<br>
-// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})<br>
-// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}})<br>
+// AArch32-LABEL: @test_wsr(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.write_register.i32(metadata !5, i32 [[V:%.*]])<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wsr(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = zext i32 [[V:%.*]] to i64<br>
+// AArch64-NEXT: call void @llvm.write_register.i64(metadata !8, i64 [[TMP0]])<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wsr(uint32_t v) {<br>
#ifdef __ARM_32BIT_STATE<br>
__arm_wsr("cp1:2:c3:c4:5", v);<br>
@@ -822,9 +1603,16 @@ void test_wsr(uint32_t v) {<br>
#endif<br>
}<br>
<br>
-// ARM-LABEL: test_wsr64<br>
-// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})<br>
-// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}})<br>
+// AArch32-LABEL: @test_wsr64(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: call void @llvm.write_register.i64(metadata !6, i64 [[V:%.*]])<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wsr64(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: call void @llvm.write_register.i64(metadata !8, i64 [[V:%.*]])<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wsr64(uint64_t v) {<br>
#ifdef __ARM_32BIT_STATE<br>
__arm_wsr64("cp1:2:c3", v);<br>
@@ -833,18 +1621,41 @@ void test_wsr64(uint64_t v) {<br>
#endif<br>
}<br>
<br>
-// ARM-LABEL: test_wsrp<br>
-// AArch64: call void @llvm.write_register.i64(metadata ![[M1:[0-9]]], i64 %{{.*}})<br>
-// AArch32: call void @llvm.write_register.i32(metadata ![[M4:[0-9]]], i32 %{{.*}})<br>
+// AArch32-LABEL: @test_wsrp(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[V:%.*]] to i32<br>
+// AArch32-NEXT: call void @llvm.write_register.i32(metadata !7, i32 [[TMP0]])<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wsrp(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[V:%.*]] to i64<br>
+// AArch64-NEXT: call void @llvm.write_register.i64(metadata !9, i64 [[TMP0]])<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wsrp(void *v) {<br>
__arm_wsrp("sysreg", v);<br>
}<br>
<br>
-// ARM-LABEL: test_rsrf<br>
-// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])<br>
-// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]])<br>
-// ARM-NOT: uitofp<br>
-// ARM: bitcast<br>
+// AArch32-LABEL: @test_rsrf(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata !5)<br>
+// AArch32-NEXT: store i32 [[TMP0]], i32* [[REF_TMP]], align 4<br>
+// AArch32-NEXT: [[TMP1:%.*]] = bitcast i32* [[REF_TMP]] to float*<br>
+// AArch32-NEXT: [[TMP2:%.*]] = load float, float* [[TMP1]], align 4<br>
+// AArch32-NEXT: ret float [[TMP2]]<br>
+//<br>
+// AArch64-LABEL: @test_rsrf(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !8)<br>
+// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32<br>
+// AArch64-NEXT: store i32 [[TMP1]], i32* [[REF_TMP]], align 4<br>
+// AArch64-NEXT: [[TMP2:%.*]] = bitcast i32* [[REF_TMP]] to float*<br>
+// AArch64-NEXT: [[TMP3:%.*]] = load float, float* [[TMP2]], align 4<br>
+// AArch64-NEXT: ret float [[TMP3]]<br>
+//<br>
float test_rsrf() {<br>
#ifdef __ARM_32BIT_STATE<br>
return __arm_rsrf("cp1:2:c3:c4:5");<br>
@@ -852,11 +1663,25 @@ float test_rsrf() {<br>
return __arm_rsrf("1:2:3:4:5");<br>
#endif<br>
}<br>
-// ARM-LABEL: test_rsrf64<br>
-// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])<br>
-// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]])<br>
-// ARM-NOT: uitofp<br>
-// ARM: bitcast<br>
+<br>
+// AArch32-LABEL: @test_rsrf64(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8<br>
+// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !6)<br>
+// AArch32-NEXT: store i64 [[TMP0]], i64* [[REF_TMP]], align 8<br>
+// AArch32-NEXT: [[TMP1:%.*]] = bitcast i64* [[REF_TMP]] to double*<br>
+// AArch32-NEXT: [[TMP2:%.*]] = load double, double* [[TMP1]], align 8<br>
+// AArch32-NEXT: ret double [[TMP2]]<br>
+//<br>
+// AArch64-LABEL: @test_rsrf64(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8<br>
+// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata !8)<br>
+// AArch64-NEXT: store i64 [[TMP0]], i64* [[REF_TMP]], align 8<br>
+// AArch64-NEXT: [[TMP1:%.*]] = bitcast i64* [[REF_TMP]] to double*<br>
+// AArch64-NEXT: [[TMP2:%.*]] = load double, double* [[TMP1]], align 8<br>
+// AArch64-NEXT: ret double [[TMP2]]<br>
+//<br>
double test_rsrf64() {<br>
#ifdef __ARM_32BIT_STATE<br>
return __arm_rsrf64("cp1:2:c3");<br>
@@ -864,11 +1689,26 @@ double test_rsrf64() {<br>
return __arm_rsrf64("1:2:3:4:5");<br>
#endif<br>
}<br>
-// ARM-LABEL: test_wsrf<br>
-// ARM-NOT: fptoui<br>
-// ARM: bitcast<br>
-// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})<br>
-// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}})<br>
+<br>
+// AArch32-LABEL: @test_wsrf(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[V_ADDR:%.*]] = alloca float, align 4<br>
+// AArch32-NEXT: store float [[V:%.*]], float* [[V_ADDR]], align 4<br>
+// AArch32-NEXT: [[TMP0:%.*]] = bitcast float* [[V_ADDR]] to i32*<br>
+// AArch32-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4<br>
+// AArch32-NEXT: call void @llvm.write_register.i32(metadata !5, i32 [[TMP1]])<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wsrf(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[V_ADDR:%.*]] = alloca float, align 4<br>
+// AArch64-NEXT: store float [[V:%.*]], float* [[V_ADDR]], align 4<br>
+// AArch64-NEXT: [[TMP0:%.*]] = bitcast float* [[V_ADDR]] to i32*<br>
+// AArch64-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4<br>
+// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64<br>
+// AArch64-NEXT: call void @llvm.write_register.i64(metadata !8, i64 [[TMP2]])<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wsrf(float v) {<br>
#ifdef __ARM_32BIT_STATE<br>
__arm_wsrf("cp1:2:c3:c4:5", v);<br>
@@ -876,11 +1716,25 @@ void test_wsrf(float v) {<br>
__arm_wsrf("1:2:3:4:5", v);<br>
#endif<br>
}<br>
-// ARM-LABEL: test_wsrf64<br>
-// ARM-NOT: fptoui<br>
-// ARM: bitcast<br>
-// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})<br>
-// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}})<br>
+<br>
+// AArch32-LABEL: @test_wsrf64(<br>
+// AArch32-NEXT: entry:<br>
+// AArch32-NEXT: [[V_ADDR:%.*]] = alloca double, align 8<br>
+// AArch32-NEXT: store double [[V:%.*]], double* [[V_ADDR]], align 8<br>
+// AArch32-NEXT: [[TMP0:%.*]] = bitcast double* [[V_ADDR]] to i64*<br>
+// AArch32-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8<br>
+// AArch32-NEXT: call void @llvm.write_register.i64(metadata !6, i64 [[TMP1]])<br>
+// AArch32-NEXT: ret void<br>
+//<br>
+// AArch64-LABEL: @test_wsrf64(<br>
+// AArch64-NEXT: entry:<br>
+// AArch64-NEXT: [[V_ADDR:%.*]] = alloca double, align 8<br>
+// AArch64-NEXT: store double [[V:%.*]], double* [[V_ADDR]], align 8<br>
+// AArch64-NEXT: [[TMP0:%.*]] = bitcast double* [[V_ADDR]] to i64*<br>
+// AArch64-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8<br>
+// AArch64-NEXT: call void @llvm.write_register.i64(metadata !8, i64 [[TMP1]])<br>
+// AArch64-NEXT: ret void<br>
+//<br>
void test_wsrf64(double v) {<br>
#ifdef __ARM_32BIT_STATE<br>
__arm_wsrf64("cp1:2:c3", v);<br>
@@ -889,17 +1743,20 @@ void test_wsrf64(double v) {<br>
#endif<br>
}<br>
<br>
-// AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"}<br>
-// AArch32: ![[M3]] = !{!"cp1:2:c3"}<br>
-// AArch32: ![[M4]] = !{!"sysreg"}<br>
-<br>
-// AArch64: ![[M0]] = !{!"1:2:3:4:5"}<br>
-// AArch64: ![[M1]] = !{!"sysreg"}<br>
-<br>
-// AArch64-v8_3-LABEL: @test_jcvt(<br>
-// AArch64-v8_3: call i32 @llvm.aarch64.fjcvtzs<br>
#ifdef __ARM_64BIT_STATE<br>
+// AArch6483-LABEL: @test_jcvt(<br>
+// AArch6483-NEXT: entry:<br>
+// AArch6483-NEXT: [[TMP0:%.*]] = call i32 @llvm.aarch64.fjcvtzs(double [[V:%.*]]) [[ATTR3:#.*]]<br>
+// AArch6483-NEXT: ret i32 [[TMP0]]<br>
+//<br>
int32_t test_jcvt(double v) {<br>
return __jcvt(v);<br>
}<br>
#endif<br>
+<br>
+// AArch32: !5 = !{!"cp1:2:c3:c4:5"}<br>
+// AArch32: !6 = !{!"cp1:2:c3"}<br>
+// AArch32: !7 = !{!"sysreg"}<br>
+<br>
+// AArch64: !8 = !{!"1:2:3:4:5"}<br>
+// AArch64: !9 = !{!"sysreg"}<br>
\ No newline at end of file<br>
<br>
<br>
<br>
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</blockquote></div>
</blockquote></div>