<div dir="ltr">Hi Alexey,<div><br></div>The new test "declare_simd_aarch64_sve.c" intermittently fails when the git revision contains "a01".<div><br></div>.../llvm/tools/clang/test/OpenMP/declare_simd_aarch64_sve.c:38:15: error: CHECK-NOT: excluded string found in input<div>// CHECK-NOT: a01</div><div> ^</div><div><stdin>:75:102: note: found here</div><div>!1 = !{!"clang version 9.0.0 (<repo>.git 60d61fe3f64a01de5ac24f6c17cddb391ec3e02c)"}<br></div><div><div> ^~~</div></div><div><br></div><div>I reckon this will fail about 1 in 100 times when built from a git repository.</div><div><br></div><div>Please could you improve the test to avoid this issue?</div><div><br></div><div>Thanks</div><div>Russ</div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, 16 Apr 2019 at 14:54, Alexey Bataev via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org">cfe-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: abataev<br>
Date: Tue Apr 16 06:56:21 2019<br>
New Revision: 358490<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=358490&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=358490&view=rev</a><br>
Log:<br>
[AArch64] Implement Vector Funtion ABI name mangling.<br>
<br>
Summary:<br>
The name mangling scheme is defined in section 3.5 of the "Vector function application binary interface specification for AArch64" [1].<br>
<br>
[1] <a href="https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi" rel="noreferrer" target="_blank">https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi</a><br>
<br>
Reviewers: rengolin, ABataev<br>
<br>
Reviewed By: ABataev<br>
<br>
Subscribers: sdesmalen, javed.absar, kristof.beyls, jdoerfert, llvm-commits<br>
<br>
Tags: #llvm<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D60583" rel="noreferrer" target="_blank">https://reviews.llvm.org/D60583</a><br>
<br>
Added:<br>
cfe/trunk/test/OpenMP/Inputs/declare-simd-fix.h<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64.c<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64.cpp<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64_complex.c<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64_fix.c<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64_sve.c<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_advsimd.c<br>
cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_sve.c<br>
Modified:<br>
cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp<br>
<br>
Modified: cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp?rev=358490&r1=358489&r2=358490&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp?rev=358490&r1=358489&r2=358490&view=diff</a><br>
==============================================================================<br>
--- cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp (original)<br>
+++ cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp Tue Apr 16 06:56:21 2019<br>
@@ -9648,6 +9648,307 @@ emitX86DeclareSimdFunction(const Functio<br>
}<br>
}<br>
<br>
+// This are the Functions that are needed to mangle the name of the<br>
+// vector functions generated by the compiler, according to the rules<br>
+// defined in the "Vector Function ABI specifications for AArch64",<br>
+// available at<br>
+// <a href="https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi" rel="noreferrer" target="_blank">https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi</a>.<br>
+<br>
+/// Maps To Vector (MTV), as defined in 3.1.1 of the AAVFABI.<br>
+///<br>
+/// TODO: Need to implement the behavior for reference marked with a<br>
+/// var or no linear modifiers (1.b in the section). For this, we<br>
+/// need to extend ParamKindTy to support the linear modifiers.<br>
+static bool getAArch64MTV(QualType QT, ParamKindTy Kind) {<br>
+ QT = QT.getCanonicalType();<br>
+<br>
+ if (QT->isVoidType())<br>
+ return false;<br>
+<br>
+ if (Kind == ParamKindTy::Uniform)<br>
+ return false;<br>
+<br>
+ if (Kind == ParamKindTy::Linear)<br>
+ return false;<br>
+<br>
+ // TODO: Handle linear references with modifiers<br>
+<br>
+ if (Kind == ParamKindTy::LinearWithVarStride)<br>
+ return false;<br>
+<br>
+ return true;<br>
+}<br>
+<br>
+/// Pass By Value (PBV), as defined in 3.1.2 of the AAVFABI.<br>
+static bool getAArch64PBV(QualType QT, ASTContext &C) {<br>
+ QT = QT.getCanonicalType();<br>
+ unsigned Size = C.getTypeSize(QT);<br>
+<br>
+ // Only scalars and complex within 16 bytes wide set PVB to true.<br>
+ if (Size != 8 && Size != 16 && Size != 32 && Size != 64 && Size != 128)<br>
+ return false;<br>
+<br>
+ if (QT->isFloatingType())<br>
+ return true;<br>
+<br>
+ if (QT->isIntegerType())<br>
+ return true;<br>
+<br>
+ if (QT->isPointerType())<br>
+ return true;<br>
+<br>
+ // TODO: Add support for complex types (section 3.1.2, item 2).<br>
+<br>
+ return false;<br>
+}<br>
+<br>
+/// Computes the lane size (LS) of a return type or of an input parameter,<br>
+/// as defined by `LS(P)` in 3.2.1 of the AAVFABI.<br>
+/// TODO: Add support for references, section 3.2.1, item 1.<br>
+static unsigned getAArch64LS(QualType QT, ParamKindTy Kind, ASTContext &C) {<br>
+ if (getAArch64MTV(QT, Kind) && QT.getCanonicalType()->isPointerType()) {<br>
+ QualType PTy = QT.getCanonicalType()->getPointeeType();<br>
+ if (getAArch64PBV(PTy, C))<br>
+ return C.getTypeSize(PTy);<br>
+ }<br>
+ if (getAArch64PBV(QT, C))<br>
+ return C.getTypeSize(QT);<br>
+<br>
+ return C.getTypeSize(C.getUIntPtrType());<br>
+}<br>
+<br>
+// Get Narrowest Data Size (NDS) and Widest Data Size (WDS) from the<br>
+// signature of the scalar function, as defined in 3.2.2 of the<br>
+// AAVFABI.<br>
+static std::tuple<unsigned, unsigned, bool><br>
+getNDSWDS(const FunctionDecl *FD, ArrayRef<ParamAttrTy> ParamAttrs) {<br>
+ QualType RetType = FD->getReturnType().getCanonicalType();<br>
+<br>
+ ASTContext &C = FD->getASTContext();<br>
+<br>
+ bool OutputBecomesInput = false;<br>
+<br>
+ llvm::SmallVector<unsigned, 8> Sizes;<br>
+ if (!RetType->isVoidType()) {<br>
+ Sizes.push_back(getAArch64LS(RetType, ParamKindTy::Vector, C));<br>
+ if (!getAArch64PBV(RetType, C) && getAArch64MTV(RetType, {}))<br>
+ OutputBecomesInput = true;<br>
+ }<br>
+ for (unsigned I = 0, E = FD->getNumParams(); I < E; ++I) {<br>
+ QualType QT = FD->getParamDecl(I)->getType().getCanonicalType();<br>
+ Sizes.push_back(getAArch64LS(QT, ParamAttrs[I].Kind, C));<br>
+ }<br>
+<br>
+ assert(!Sizes.empty() && "Unable to determine NDS and WDS.");<br>
+ // The LS of a function parameter / return value can only be a power<br>
+ // of 2, starting from 8 bits, up to 128.<br>
+ assert(std::all_of(Sizes.begin(), Sizes.end(),<br>
+ [](unsigned Size) {<br>
+ return Size == 8 || Size == 16 || Size == 32 ||<br>
+ Size == 64 || Size == 128;<br>
+ }) &&<br>
+ "Invalid size");<br>
+<br>
+ return std::make_tuple(*std::min_element(std::begin(Sizes), std::end(Sizes)),<br>
+ *std::max_element(std::begin(Sizes), std::end(Sizes)),<br>
+ OutputBecomesInput);<br>
+}<br>
+<br>
+/// Mangle the parameter part of the vector function name according to<br>
+/// their OpenMP classification. The mangling function is defined in<br>
+/// section 3.5 of the AAVFABI.<br>
+static std::string mangleVectorParameters(ArrayRef<ParamAttrTy> ParamAttrs) {<br>
+ SmallString<256> Buffer;<br>
+ llvm::raw_svector_ostream Out(Buffer);<br>
+ for (const auto &ParamAttr : ParamAttrs) {<br>
+ switch (ParamAttr.Kind) {<br>
+ case LinearWithVarStride:<br>
+ Out << "ls" << ParamAttr.StrideOrArg;<br>
+ break;<br>
+ case Linear:<br>
+ Out << 'l';<br>
+ // Don't print the step value if it is not present or if it is<br>
+ // equal to 1.<br>
+ if (!!ParamAttr.StrideOrArg && ParamAttr.StrideOrArg != 1)<br>
+ Out << ParamAttr.StrideOrArg;<br>
+ break;<br>
+ case Uniform:<br>
+ Out << 'u';<br>
+ break;<br>
+ case Vector:<br>
+ Out << 'v';<br>
+ break;<br>
+ }<br>
+<br>
+ if (!!ParamAttr.Alignment)<br>
+ Out << 'a' << ParamAttr.Alignment;<br>
+ }<br>
+<br>
+ return Out.str();<br>
+}<br>
+<br>
+// Function used to add the attribute. The parameter `VLEN` is<br>
+// templated to allow the use of "x" when targeting scalable functions<br>
+// for SVE.<br>
+template <typename T><br>
+static void addAArch64VectorName(T VLEN, StringRef LMask, StringRef Prefix,<br>
+ char ISA, StringRef ParSeq,<br>
+ StringRef MangledName, bool OutputBecomesInput,<br>
+ llvm::Function *Fn) {<br>
+ SmallString<256> Buffer;<br>
+ llvm::raw_svector_ostream Out(Buffer);<br>
+ Out << Prefix << ISA << LMask << VLEN;<br>
+ if (OutputBecomesInput)<br>
+ Out << "v";<br>
+ Out << ParSeq << "_" << MangledName;<br>
+ Fn->addFnAttr(Out.str());<br>
+}<br>
+<br>
+// Helper function to generate the Advanced SIMD names depending on<br>
+// the value of the NDS when simdlen is not present.<br>
+static void addAArch64AdvSIMDNDSNames(unsigned NDS, StringRef Mask,<br>
+ StringRef Prefix, char ISA,<br>
+ StringRef ParSeq, StringRef MangledName,<br>
+ bool OutputBecomesInput,<br>
+ llvm::Function *Fn) {<br>
+ switch (NDS) {<br>
+ case 8:<br>
+ addAArch64VectorName(8, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ addAArch64VectorName(16, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case 16:<br>
+ addAArch64VectorName(4, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ addAArch64VectorName(8, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case 32:<br>
+ addAArch64VectorName(2, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ addAArch64VectorName(4, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case 64:<br>
+ case 128:<br>
+ addAArch64VectorName(2, Mask, Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ default:<br>
+ llvm_unreachable("Scalar type is too wide.");<br>
+ }<br>
+}<br>
+<br>
+/// Emit vector function attributes for AArch64, as defined in the AAVFABI.<br>
+static void emitAArch64DeclareSimdFunction(<br>
+ CodeGenModule &CGM, const FunctionDecl *FD, unsigned UserVLEN,<br>
+ ArrayRef<ParamAttrTy> ParamAttrs,<br>
+ OMPDeclareSimdDeclAttr::BranchStateTy State, StringRef MangledName,<br>
+ char ISA, unsigned VecRegSize, llvm::Function *Fn, SourceLocation SLoc) {<br>
+<br>
+ // Get basic data for building the vector signature.<br>
+ const auto Data = getNDSWDS(FD, ParamAttrs);<br>
+ const unsigned NDS = std::get<0>(Data);<br>
+ const unsigned WDS = std::get<1>(Data);<br>
+ const bool OutputBecomesInput = std::get<2>(Data);<br>
+<br>
+ // Check the values provided via `simdlen` by the user.<br>
+ // 1. A `simdlen(1)` doesn't produce vector signatures,<br>
+ if (UserVLEN == 1) {<br>
+ unsigned DiagID = CGM.getDiags().getCustomDiagID(<br>
+ DiagnosticsEngine::Warning,<br>
+ "The clause simdlen(1) has no effect when targeting aarch64.");<br>
+ CGM.getDiags().Report(SLoc, DiagID);<br>
+ return;<br>
+ }<br>
+<br>
+ // 2. Section 3.3.1, item 1: user input must be a power of 2 for<br>
+ // Advanced SIMD output.<br>
+ if (ISA == 'n' && UserVLEN && !llvm::isPowerOf2_32(UserVLEN)) {<br>
+ unsigned DiagID = CGM.getDiags().getCustomDiagID(<br>
+ DiagnosticsEngine::Warning, "The value specified in simdlen must be a "<br>
+ "power of 2 when targeting Advanced SIMD.");<br>
+ CGM.getDiags().Report(SLoc, DiagID);<br>
+ return;<br>
+ }<br>
+<br>
+ // 3. Section 3.4.1. SVE fixed lengh must obey the architectural<br>
+ // limits.<br>
+ if (ISA == 's' && UserVLEN != 0) {<br>
+ if ((UserVLEN * WDS > 2048) || (UserVLEN * WDS % 128 != 0)) {<br>
+ unsigned DiagID = CGM.getDiags().getCustomDiagID(<br>
+ DiagnosticsEngine::Warning, "The clause simdlen must fit the %0-bit "<br>
+ "lanes in the architectural constraints "<br>
+ "for SVE (min is 128-bit, max is "<br>
+ "2048-bit, by steps of 128-bit)");<br>
+ CGM.getDiags().Report(SLoc, DiagID) << WDS;<br>
+ return;<br>
+ }<br>
+ }<br>
+<br>
+ // Sort out parameter sequence.<br>
+ const std::string ParSeq = mangleVectorParameters(ParamAttrs);<br>
+ StringRef Prefix = "_ZGV";<br>
+ // Generate simdlen from user input (if any).<br>
+ if (UserVLEN) {<br>
+ if (ISA == 's') {<br>
+ // SVE generates only a masked function.<br>
+ addAArch64VectorName(UserVLEN, "M", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ } else {<br>
+ assert(ISA == 'n' && "Expected ISA either 's' or 'n'.");<br>
+ // Advanced SIMD generates one or two functions, depending on<br>
+ // the `[not]inbranch` clause.<br>
+ switch (State) {<br>
+ case OMPDeclareSimdDeclAttr::BS_Undefined:<br>
+ addAArch64VectorName(UserVLEN, "N", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ addAArch64VectorName(UserVLEN, "M", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case OMPDeclareSimdDeclAttr::BS_Notinbranch:<br>
+ addAArch64VectorName(UserVLEN, "N", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case OMPDeclareSimdDeclAttr::BS_Inbranch:<br>
+ addAArch64VectorName(UserVLEN, "M", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ }<br>
+ }<br>
+ } else {<br>
+ // If no user simdlen is provided, follow the AAVFABI rules for<br>
+ // generating the vector length.<br>
+ if (ISA == 's') {<br>
+ // SVE, section 3.4.1, item 1.<br>
+ addAArch64VectorName("x", "M", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ } else {<br>
+ assert(ISA == 'n' && "Expected ISA either 's' or 'n'.");<br>
+ // Advanced SIMD, Section 3.3.1 of the AAVFABI, generates one or<br>
+ // two vector names depending on the use of the clause<br>
+ // `[not]inbranch`.<br>
+ switch (State) {<br>
+ case OMPDeclareSimdDeclAttr::BS_Undefined:<br>
+ addAArch64AdvSIMDNDSNames(NDS, "N", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ addAArch64AdvSIMDNDSNames(NDS, "M", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case OMPDeclareSimdDeclAttr::BS_Notinbranch:<br>
+ addAArch64AdvSIMDNDSNames(NDS, "N", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ case OMPDeclareSimdDeclAttr::BS_Inbranch:<br>
+ addAArch64AdvSIMDNDSNames(NDS, "M", Prefix, ISA, ParSeq, MangledName,<br>
+ OutputBecomesInput, Fn);<br>
+ break;<br>
+ }<br>
+ }<br>
+ }<br>
+}<br>
+<br>
void CGOpenMPRuntime::emitDeclareSimdFunction(const FunctionDecl *FD,<br>
llvm::Function *Fn) {<br>
ASTContext &C = CGM.getContext();<br>
@@ -9734,12 +10035,26 @@ void CGOpenMPRuntime::emitDeclareSimdFun<br>
++MI;<br>
}<br>
llvm::APSInt VLENVal;<br>
- if (const Expr *VLEN = Attr->getSimdlen())<br>
- VLENVal = VLEN->EvaluateKnownConstInt(C);<br>
+ SourceLocation ExprLoc;<br>
+ const Expr *VLENExpr = Attr->getSimdlen();<br>
+ if (VLENExpr) {<br>
+ VLENVal = VLENExpr->EvaluateKnownConstInt(C);<br>
+ ExprLoc = VLENExpr->getExprLoc();<br>
+ }<br>
OMPDeclareSimdDeclAttr::BranchStateTy State = Attr->getBranchState();<br>
if (CGM.getTriple().getArch() == llvm::Triple::x86 ||<br>
- CGM.getTriple().getArch() == llvm::Triple::x86_64)<br>
+ CGM.getTriple().getArch() == llvm::Triple::x86_64) {<br>
emitX86DeclareSimdFunction(FD, Fn, VLENVal, ParamAttrs, State);<br>
+ } else if (CGM.getTriple().getArch() == llvm::Triple::aarch64) {<br>
+ unsigned VLEN = VLENVal.getExtValue();<br>
+ StringRef MangledName = Fn->getName();<br>
+ if (CGM.getTarget().hasFeature("sve"))<br>
+ emitAArch64DeclareSimdFunction(CGM, FD, VLEN, ParamAttrs, State,<br>
+ MangledName, 's', 128, Fn, ExprLoc);<br>
+ if (CGM.getTarget().hasFeature("neon"))<br>
+ emitAArch64DeclareSimdFunction(CGM, FD, VLEN, ParamAttrs, State,<br>
+ MangledName, 'n', 128, Fn, ExprLoc);<br>
+ }<br>
}<br>
FD = FD->getPreviousDecl();<br>
}<br>
<br>
Added: cfe/trunk/test/OpenMP/Inputs/declare-simd-fix.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/Inputs/declare-simd-fix.h?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/Inputs/declare-simd-fix.h?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/Inputs/declare-simd-fix.h (added)<br>
+++ cfe/trunk/test/OpenMP/Inputs/declare-simd-fix.h Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,8 @@<br>
+#ifndef LLVM_CLANG_TEST_OPENMP_INPUTS_DECLARE_SIMD_FIX_H<br>
+#define LLVM_CLANG_TEST_OPENMP_INPUTS_DECLARE_SIMD_FIX_H<br>
+<br>
+#pragma omp declare simd<br>
+float foo(float a, float b, int c);<br>
+float bar(float a, float b, int c);<br>
+<br>
+#endif<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64.c?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64.c?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64.c (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64.c Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,190 @@<br>
+// -fopemp and -fopenmp-simd behavior are expected to be the same.<br>
+<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -fopenmp -x c -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=AARCH64<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -fopenmp-simd -x c -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=AARCH64<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd simdlen(2)<br>
+#pragma omp declare simd simdlen(6)<br>
+#pragma omp declare simd simdlen(8)<br>
+double foo(float x);<br>
+<br>
+// AARCH64: "_ZGVnM2v_foo" "_ZGVnM4v_foo" "_ZGVnM8v_foo" "_ZGVnN2v_foo" "_ZGVnN4v_foo" "_ZGVnN8v_foo"<br>
+// AARCH64-NOT: _ZGVnN6v_foo<br>
+<br>
+void foo_loop(double *x, float *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = foo(y[i]);<br>
+ }<br>
+}<br>
+<br>
+// make sure that the following two function by default gets generated<br>
+// with 4 and 2 lanes, as descrived in the vector ABI<br>
+#pragma omp declare simd notinbranch<br>
+float bar(double x);<br>
+#pragma omp declare simd notinbranch<br>
+double baz(float x);<br>
+<br>
+// AARCH64: "_ZGVnN2v_baz" "_ZGVnN4v_baz"<br>
+// AARCH64-NOT: baz<br>
+// AARCH64: "_ZGVnN2v_bar" "_ZGVnN4v_bar"<br>
+// AARCH64-NOT: bar<br>
+<br>
+void baz_bar_loop(double *x, float *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = baz(y[i]);<br>
+ y[i] = bar(x[i]);<br>
+ }<br>
+}<br>
+<br>
+ /***************************/<br>
+ /* 32-bit integer tests */<br>
+ /***************************/<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd simdlen(2)<br>
+#pragma omp declare simd simdlen(6)<br>
+#pragma omp declare simd simdlen(8)<br>
+long foo_int(int x);<br>
+<br>
+// AARCH64: "_ZGVnN2v_foo_int" "_ZGVnN4v_foo_int" "_ZGVnN8v_foo_int"<br>
+// No non power of two<br>
+// AARCH64-NOT: _ZGVnN6v_foo_int<br>
+<br>
+void foo_int_loop(long *x, int *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = foo_int(y[i]);<br>
+ }<br>
+}<br>
+<br>
+#pragma omp declare simd<br>
+char simple_8bit(char);<br>
+// AARCH64: "_ZGVnM16v_simple_8bit" "_ZGVnM8v_simple_8bit" "_ZGVnN16v_simple_8bit" "_ZGVnN8v_simple_8bit"<br>
+#pragma omp declare simd<br>
+short simple_16bit(short);<br>
+// AARCH64: "_ZGVnM4v_simple_16bit" "_ZGVnM8v_simple_16bit" "_ZGVnN4v_simple_16bit" "_ZGVnN8v_simple_16bit"<br>
+#pragma omp declare simd<br>
+int simple_32bit(int);<br>
+// AARCH64: "_ZGVnM2v_simple_32bit" "_ZGVnM4v_simple_32bit" "_ZGVnN2v_simple_32bit" "_ZGVnN4v_simple_32bit"<br>
+#pragma omp declare simd<br>
+long simple_64bit(long);<br>
+// AARCH64: "_ZGVnM2v_simple_64bit" "_ZGVnN2v_simple_64bit"<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd simdlen(32)<br>
+char a01(int x);<br>
+// AARCH64: "_ZGVnN16v_a01" "_ZGVnN32v_a01" "_ZGVnN8v_a01"<br>
+// AARCH64-NOT: a01<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd simdlen(2)<br>
+long a02(short x);<br>
+// AARCH64: "_ZGVnN2v_a02" "_ZGVnN4v_a02" "_ZGVnN8v_a02"<br>
+<br>
+// AARCH64-NOT: a02<br>
+/************/<br>
+/* pointers */<br>
+/************/<br>
+<br>
+#pragma omp declare simd<br>
+int b01(int *x);<br>
+// AARCH64: "_ZGVnN4v_b01"<br>
+// AARCH64-NOT: b01<br>
+<br>
+#pragma omp declare simd<br>
+char b02(char *);<br>
+// AARCH64: "_ZGVnN16v_b02" "_ZGVnN8v_b02"<br>
+// AARCH64-NOT: b02<br>
+<br>
+#pragma omp declare simd<br>
+double *b03(double *);<br>
+// AARCH64: "_ZGVnN2v_b03"<br>
+// AARCH64-NOT: b03<br>
+<br>
+/***********/<br>
+/* masking */<br>
+/***********/<br>
+<br>
+#pragma omp declare simd inbranch<br>
+int c01(double *x, short y);<br>
+// AARCH64: "_ZGVnM8vv_c01"<br>
+// AARCH64-NOT: c01<br>
+<br>
+#pragma omp declare simd inbranch uniform(x)<br>
+double c02(double *x, char y);<br>
+// AARCH64: "_ZGVnM16uv_c02" "_ZGVnM8uv_c02"<br>
+// AARCH64-NOT: c02<br>
+<br>
+/*************************/<br>
+/* sincos-like signature */<br>
+/*************************/<br>
+#pragma omp declare simd linear(sin) linear(cos)<br>
+void sincos(double in, double *sin, double *cos);<br>
+// AARCH64: "_ZGVnN2vll_sincos"<br>
+// AARCH64-NOT: sincos<br>
+<br>
+#pragma omp declare simd linear(sin : 1) linear(cos : 2)<br>
+void SinCos(double in, double *sin, double *cos);<br>
+// AARCH64: "_ZGVnN2vll2_SinCos"<br>
+// AARCH64-NOT: SinCos<br>
+<br>
+// Selection of tests based on the examples provided in chapter 5 of<br>
+// the Vector Function ABI specifications for AArch64, at<br>
+// <a href="https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi" rel="noreferrer" target="_blank">https://developer.arm.com/products/software-development-tools/hpc/arm-compiler-for-hpc/vector-function-abi</a>.<br>
+<br>
+// Listing 2, p. 18<br>
+#pragma omp declare simd inbranch uniform(x) linear(val(i) : 4)<br>
+int foo2(int *x, int i);<br>
+// AARCH64: "_ZGVnM2ul4_foo2" "_ZGVnM4ul4_foo2"<br>
+// AARCH64-NOT: foo2<br>
+<br>
+// Listing 3, p. 18<br>
+#pragma omp declare simd inbranch uniform(x, c) linear(i \<br>
+ : c)<br>
+int foo3(int *x, int i, unsigned char c);<br>
+// AARCH64: "_ZGVnM16uls2u_foo3" "_ZGVnM8uls2u_foo3"<br>
+// AARCH64-NOT: foo3<br>
+<br>
+// Listing 6, p. 19<br>
+#pragma omp declare simd linear(x) aligned(x : 16) simdlen(4)<br>
+int foo4(int *x, float y);<br>
+// AARCH64: "_ZGVnM4la16v_foo4" "_ZGVnN4la16v_foo4"<br>
+// AARCH64-NOT: foo4<br>
+<br>
+static int *I;<br>
+static char *C;<br>
+static short *S;<br>
+static long *L;<br>
+static float *F;<br>
+static double *D;<br>
+void do_something() {<br>
+ simple_8bit(*C);<br>
+ simple_16bit(*S);<br>
+ simple_32bit(*I);<br>
+ simple_64bit(*L);<br>
+ *C = a01(*I);<br>
+ *L = a02(*S);<br>
+ *I = b01(I);<br>
+ *C = b02(C);<br>
+ D = b03(D);<br>
+ *I = c01(D, *S);<br>
+ *D = c02(D, *S);<br>
+ sincos(*D, D, D);<br>
+ SinCos(*D, D, D);<br>
+ foo2(I, *I);<br>
+ foo3(I, *I, *C);<br>
+ foo4(I, *F);<br>
+}<br>
+<br>
+typedef struct S {<br>
+ char R, G, B;<br>
+} STy;<br>
+#pragma omp declare simd notinbranch<br>
+STy DoRGB(STy x);<br>
+// AARCH64: "_ZGVnN2v_DoRGB"<br>
+<br>
+static STy *RGBData;<br>
+<br>
+void do_rgb_stuff() {<br>
+ DoRGB(*RGBData);<br>
+}<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64.cpp?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64.cpp?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64.cpp (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64.cpp Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,37 @@<br>
+// -fopemp and -fopenmp-simd behavior are expected to be the same.<br>
+<br>
+// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -target-feature +neon -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls -verify| FileCheck %s --check-prefix=ADVSIMD<br>
+// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -target-feature +sve -fopenmp -x c++ -emit-llvm %s -o - -femit-all-decls -verify| FileCheck %s --check-prefix=SVE<br>
+<br>
+// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -target-feature +neon -fopenmp-simd -x c++ -emit-llvm %s -o - -femit-all-decls -verify| FileCheck %s --check-prefix=ADVSIMD<br>
+// RUN: %clang_cc1 -verify -triple aarch64-linux-gnu -target-feature +sve -fopenmp-simd -x c++ -emit-llvm %s -o - -femit-all-decls -verify| FileCheck %s --check-prefix=SVE<br>
+<br>
+// expected-no-diagnostics<br>
+<br>
+#pragma omp declare simd<br>
+double f(double x);<br>
+<br>
+#pragma omp declare simd<br>
+float f(float x);<br>
+<br>
+void aaa(double *x, double *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = f(y[i]);<br>
+ }<br>
+}<br>
+<br>
+void aaa(float *x, float *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = f(y[i]);<br>
+ }<br>
+}<br>
+<br>
+// ADVSIMD: "_ZGVnN2v__Z1fd"<br>
+// ADVSIMD-NOT: _Z1fd<br>
+// ADVSIMD: "_ZGVnN4v__Z1ff"<br>
+// ADVSIMD-NOT: _Z1fF<br>
+<br>
+// SVE: "_ZGVsMxv__Z1fd"<br>
+// SVE-NOT: _Z1fd<br>
+// SVE: "_ZGVsMxv__Z1ff"<br>
+// SVE-NOT: _Z1ff<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64_complex.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_complex.c?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_complex.c?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64_complex.c (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64_complex.c Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,26 @@<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -fopenmp -x c -std=c11 -emit-llvm %s -o - -femit-all-decls | FileCheck %s<br>
+<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve -fopenmp -x c -std=c11 -emit-llvm %s -o - -femit-all-decls | FileCheck %s --check-prefix=SVE<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd simdlen(4) notinbranch<br>
+double _Complex double_complex(double _Complex);<br>
+// CHECK: "_ZGVnM2v_double_complex" "_ZGVnN2v_double_complex" "_ZGVnN4v_double_complex"<br>
+// CHECK-NOT: double_complex<br>
+// SVE: "_ZGVsM4v_double_complex" "_ZGVsMxv_double_complex"<br>
+// SVE-NOT: double_complex<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd simdlen(8) notinbranch<br>
+float _Complex float_complex(float _Complex);<br>
+// CHECK: "_ZGVnM2v_float_complex" "_ZGVnN2v_float_complex" "_ZGVnN8v_float_complex"<br>
+// CHECK-NOT: float_complex<br>
+// SVE: "_ZGVsM8v_float_complex" "_ZGVsMxv_float_complex"<br>
+// SVE-NOT: float_complex<br>
+<br>
+static double _Complex *DC;<br>
+static float _Complex *DF;<br>
+void call_the_complex_functions() {<br>
+ double_complex(*DC);<br>
+ float_complex(*DF);<br>
+}<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64_fix.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_fix.c?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_fix.c?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64_fix.c (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64_fix.c Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,37 @@<br>
+// This test is making sure that no crash happens.<br>
+<br>
+// RUN: %clang -o - -fno-fast-math -S -target aarch64-linux-gnu \<br>
+// RUN: -fopenmp -O3 -march=armv8-a -c %s | FileCheck %s<br>
+<br>
+// RUN: %clang -o - -fno-fast-math -S -target aarch64-linux-gnu \<br>
+// RUN: -fopenmp-simd -O3 -march=armv8-a -c %s | FileCheck %s<br>
+<br>
+// RUN: %clang -o - -fno-fast-math -S -target aarch64-linux-gnu \<br>
+// RUN: -fopenmp -O3 -march=armv8-a+sve -c %s | FileCheck %s<br>
+<br>
+// RUN: %clang -o - -fno-fast-math -S -target aarch64-linux-gnu \<br>
+// RUN: -fopenmp-simd -O3 -march=armv8-a+sve -c %s | FileCheck %s<br>
+<br>
+// loop in the user code, in user_code.c<br>
+#include "Inputs/declare-simd-fix.h"<br>
+<br>
+// CHECK-LABEL: do_something:<br>
+void do_something(int *a, double *b, unsigned N) {<br>
+ for (unsigned i = 0; i < N; ++i) {<br>
+ a[i] = foo(b[0], b[0], 1);<br>
+ }<br>
+}<br>
+<br>
+// CHECK-LABEL: do_something_else:<br>
+void do_something_else(int *a, double *b, unsigned N) {<br>
+ for (unsigned i = 0; i < N; ++i) {<br>
+ a[i] = foo(1.1, 1.2, 1);<br>
+ }<br>
+}<br>
+<br>
+// CHECK-LABEL: do_something_more:<br>
+void do_something_more(int *a, double *b, unsigned N) {<br>
+ for (unsigned i = 0; i < N; ++i) {<br>
+ a[i] = foo(b[i], b[i], a[1]);<br>
+ }<br>
+}<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64_sve.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_sve.c?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_sve.c?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64_sve.c (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64_sve.c Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,43 @@<br>
+// -fopemp and -fopenmp-simd behavior are expected to be the same<br>
+<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve \<br>
+// RUN: -fopenmp -x c -emit-llvm %s -o - -femit-all-decls | FileCheck %s<br>
+<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve \<br>
+// RUN: -fopenmp-simd -x c -emit-llvm %s -o - -femit-all-decls | FileCheck %s<br>
+<br>
+#pragma omp declare simd<br>
+#pragma omp declare simd notinbranch<br>
+#pragma omp declare simd simdlen(2)<br>
+#pragma omp declare simd simdlen(4)<br>
+#pragma omp declare simd simdlen(5) // not a multiple of 128-bits<br>
+#pragma omp declare simd simdlen(6)<br>
+#pragma omp declare simd simdlen(8)<br>
+#pragma omp declare simd simdlen(32)<br>
+#pragma omp declare simd simdlen(34) // requires more than 2048 bits<br>
+double foo(float x);<br>
+<br>
+// CHECK-DAG: "_ZGVsM2v_foo" "_ZGVsM32v_foo" "_ZGVsM4v_foo" "_ZGVsM6v_foo" "_ZGVsM8v_foo" "_ZGVsMxv_foo"<br>
+// CHECK-NOT: _ZGVsN<br>
+// CHECK-NOT: _ZGVsM5v_foo<br>
+// CHECK-NOT: _ZGVsM34v_foo<br>
+// CHECK-NOT: foo<br>
+<br>
+void foo_loop(double *x, float *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = foo(y[i]);<br>
+ }<br>
+}<br>
+<br>
+ // test integers<br>
+<br>
+#pragma omp declare simd notinbranch<br>
+char a01(int x);<br>
+// CHECK-DAG: _ZGVsMxv_a01<br>
+// CHECK-NOT: a01<br>
+<br>
+static int *in;<br>
+static char *out;<br>
+void do_something() {<br>
+ *out = a01(*in);<br>
+}<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_advsimd.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_advsimd.c?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_advsimd.c?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_advsimd.c (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_advsimd.c Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,16 @@<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -fopenmp %s -S -o %t -verify<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -fopenmp-simd %s -S -o %t -verify<br>
+<br>
+#pragma omp declare simd simdlen(6)<br>
+double foo(float x);<br>
+// expected-warning@-2{{The value specified in simdlen must be a power of 2 when targeting Advanced SIMD.}}<br>
+#pragma omp declare simd simdlen(1)<br>
+float bar(double x);<br>
+// expected-warning@-2{{The clause simdlen(1) has no effect when targeting aarch64.}}<br>
+<br>
+void foo_loop(double *x, float *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = foo(y[i]);<br>
+ y[i] = bar(x[i]);<br>
+ }<br>
+}<br>
<br>
Added: cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_sve.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_sve.c?rev=358490&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_sve.c?rev=358490&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_sve.c (added)<br>
+++ cfe/trunk/test/OpenMP/declare_simd_aarch64_warning_sve.c Tue Apr 16 06:56:21 2019<br>
@@ -0,0 +1,12 @@<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve -fopenmp %s -S -o %t -verify<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +sve -fopenmp-simd %s -S -o %t -verify<br>
+<br>
+#pragma omp declare simd simdlen(66)<br>
+double foo(float x);<br>
+//expected-warning@-2{{The clause simdlen must fit the 64-bit lanes in the architectural constraints for SVE (min is 128-bit, max is 2048-bit, by steps of 128-bit)}}<br>
+<br>
+void foo_loop(double *x, float *y, int N) {<br>
+ for (int i = 0; i < N; ++i) {<br>
+ x[i] = foo(y[i]);<br>
+ }<br>
+}<br>
<br>
<br>
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</blockquote></div>