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<p>Hi.</p>
<p><br>
</p>
<p>I fixed the tests</p>
<p>- union-align.c and bool_casts.cl</p>
<p>Did you mean this error now:</p>
<p><br>
</p>
<p></p>
<pre class="console-output" style="box-sizing: border-box; white-space: pre-wrap; word-wrap: break-word; margin-top: 0px; margin-bottom: 0px; color: rgb(51, 51, 51); font-size: 13px;">FAILED: lib/Target/ARM/ARMGenGlobalISel.inc.tmp "</pre>
<pre class="console-output" style="box-sizing: border-box; white-space: pre-wrap; word-wrap: break-word; margin-top: 0px; margin-bottom: 0px; color: rgb(51, 51, 51); font-size: 13px;"><br></pre>
<pre class="console-output" style="box-sizing: border-box; white-space: pre-wrap; word-wrap: break-word; margin-top: 0px; margin-bottom: 0px; color: rgb(51, 51, 51); font-size: 13px;">because that doesn't seem related to alignment fix.</pre>
<pre class="console-output" style="box-sizing: border-box; white-space: pre-wrap; word-wrap: break-word; margin-top: 0px; margin-bottom: 0px; color: rgb(51, 51, 51); font-size: 13px;">Thanks</pre>
<pre class="console-output" style="box-sizing: border-box; white-space: pre-wrap; word-wrap: break-word; margin-top: 0px; margin-bottom: 0px; color: rgb(51, 51, 51); font-size: 13px;">Javed</pre>
<p></p>
<p><br>
</p>
<br>
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<hr tabindex="-1" style="display:inline-block; width:98%">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> vsk@apple.com <vsk@apple.com> on behalf of Vedant Kumar <vsk@apple.com><br>
<b>Sent:</b> 30 May 2017 17:06<br>
<b>To:</b> Javed Absar<br>
<b>Cc:</b> cfe-commits; Diana Picus<br>
<b>Subject:</b> Re: r304201 - [ARM] Fix Neon vector type alignment to 64-bit</font>
<div> </div>
</div>
<div>Hi,
<div class=""><br class="">
</div>
<div class="">
<div class="">I think this change is responsible for a tablgen failure in stage2 builds:</div>
<div class=""><br class="">
</div>
<div class=""> <a href="http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/2171/" class="">http://green.lab.llvm.org/green/job/clang-stage2-configure-Rthinlto_build/2171/</a></div>
<div class=""><br class="">
</div>
<div class=""><br class="">
</div>
<div>
<blockquote type="cite" class="">
<div class="">On May 30, 2017, at 4:59 AM, Diana Picus via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org" class="">cfe-commits@lists.llvm.org</a>> wrote:</div>
<br class="Apple-interchange-newline">
<div class="">
<div class="">Hi Javed,<br class="">
<br class="">
I think this broke the bots:<br class="">
<a href="http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/7620" class="">http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/7620</a><br class="">
<br class="">
Can you have a look, or revert?<br class="">
</div>
</div>
</blockquote>
<div><br class="">
</div>
<div>+ 1</div>
<div><br class="">
</div>
<div>best,</div>
<div>vedant</div>
<br class="">
<blockquote type="cite" class="">
<div class="">
<div class=""><br class="">
Thanks,<br class="">
Diana<br class="">
<br class="">
On 30 May 2017 at 12:12, Javed Absar via cfe-commits<br class="">
<<a href="mailto:cfe-commits@lists.llvm.org" class="">cfe-commits@lists.llvm.org</a>> wrote:<br class="">
<blockquote type="cite" class="">Author: javed.absar<br class="">
Date: Tue May 30 05:12:15 2017<br class="">
New Revision: 304201<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=304201&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=304201&view=rev</a><br class="">
Log:<br class="">
[ARM] Fix Neon vector type alignment to 64-bit<br class="">
<br class="">
The maximum alignment for ARM NEON data types should be 64-bits as specified<br class="">
in ARM procedure call standard document Sec. A.2 Notes.<br class="">
This patch fixes it from its current larger natural default values, except<br class="">
for Android (so as not to break existing ABI).<br class="">
Reviewed by: Stephen Hines, Renato Golin.<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D33205" class="">https://reviews.llvm.org/D33205</a><br class="">
<br class="">
<br class="">
Modified:<br class="">
cfe/trunk/lib/Basic/Targets.cpp<br class="">
cfe/trunk/test/CodeGen/arm-abi-vector.c<br class="">
cfe/trunk/test/CodeGen/arm-neon-misc.c<br class="">
cfe/trunk/test/CodeGen/arm-swiftcall.c<br class="">
cfe/trunk/test/CodeGen/armv7k-abi.c<br class="">
<br class="">
Modified: cfe/trunk/lib/Basic/Targets.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304201&r1=304200&r2=304201&view=diff" class="">
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=304201&r1=304200&r2=304201&view=diff</a><br class="">
==============================================================================<br class="">
--- cfe/trunk/lib/Basic/Targets.cpp (original)<br class="">
+++ cfe/trunk/lib/Basic/Targets.cpp Tue May 30 05:12:15 2017<br class="">
@@ -5382,6 +5382,11 @@ public:<br class="">
// ARM has atomics up to 8 bytes<br class="">
setAtomic();<br class="">
<br class="">
+ if (Triple.getEnvironment() == llvm::Triple::Android)<br class="">
+ MaxVectorAlign = 128; // don't break existing Android ABI<br class="">
+ else<br class="">
+ MaxVectorAlign = 64; // AAPCS<br class="">
+<br class="">
// Do force alignment of members that follow zero length bitfields. If<br class="">
// the alignment of the zero-length bitfield is greater than the member<br class="">
// that follows it, `bar', `bar' will be aligned as the type of the<br class="">
<br class="">
Modified: cfe/trunk/test/CodeGen/arm-abi-vector.c<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-abi-vector.c?rev=304201&r1=304200&r2=304201&view=diff" class="">
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-abi-vector.c?rev=304201&r1=304200&r2=304201&view=diff</a><br class="">
==============================================================================<br class="">
--- cfe/trunk/test/CodeGen/arm-abi-vector.c (original)<br class="">
+++ cfe/trunk/test/CodeGen/arm-abi-vector.c Tue May 30 05:12:15 2017<br class="">
@@ -133,20 +133,20 @@ double test_5c(__char5 *in) {<br class="">
<br class="">
double varargs_vec_9c(int fixed, ...) {<br class="">
// CHECK: varargs_vec_9c<br class="">
-// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 16<br class="">
+// CHECK: [[VAR:%.*]] = alloca <9 x i8>, align 8<br class="">
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8<br class="">
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*<br class="">
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16<br class="">
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <9 x i8>*<br class="">
// CHECK: [[T0:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 8<br class="">
-// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 16<br class="">
+// CHECK: store <9 x i8> [[T0]], <9 x i8>* [[VAR]], align 8<br class="">
// APCS-GNU: varargs_vec_9c<br class="">
-// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 16<br class="">
+// APCS-GNU: [[VAR:%.*]] = alloca <9 x i8>, align 8<br class="">
// APCS-GNU: [[AP:%.*]] = load i8*,<br class="">
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16<br class="">
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <9 x i8>*<br class="">
// APCS-GNU: [[VEC:%.*]] = load <9 x i8>, <9 x i8>* [[AP_CAST]], align 4<br class="">
-// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 16<br class="">
+// APCS-GNU: store <9 x i8> [[VEC]], <9 x i8>* [[VAR]], align 8<br class="">
// ANDROID: varargs_vec_9c<br class="">
// ANDROID: [[VAR:%.*]] = alloca <9 x i8>, align 16<br class="">
// ANDROID: [[ALIGN:%.*]] = and i32 {{%.*}}, -8<br class="">
@@ -246,15 +246,15 @@ double test_3s(__short3 *in) {<br class="">
<br class="">
double varargs_vec_5s(int fixed, ...) {<br class="">
// CHECK: varargs_vec_5s<br class="">
-// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 16<br class="">
+// CHECK: [[VAR_ALIGN:%.*]] = alloca <5 x i16>, align 8<br class="">
// CHECK: [[ALIGN:%.*]] = and i32 {{%.*}}, -8<br class="">
// CHECK: [[AP_ALIGN:%.*]] = inttoptr i32 [[ALIGN]] to i8*<br class="">
// CHECK: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP_ALIGN]], i32 16<br class="">
// CHECK: [[AP_CAST:%.*]] = bitcast i8* [[AP_ALIGN]] to <5 x i16>*<br class="">
// CHECK: [[VEC:%.*]] = load <5 x i16>, <5 x i16>* [[AP_CAST]], align 8<br class="">
-// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 16<br class="">
+// CHECK: store <5 x i16> [[VEC]], <5 x i16>* [[VAR_ALIGN]], align 8<br class="">
// APCS-GNU: varargs_vec_5s<br class="">
-// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 16<br class="">
+// APCS-GNU: [[VAR:%.*]] = alloca <5 x i16>, align 8<br class="">
// APCS-GNU: [[AP:%.*]] = load i8*,<br class="">
// APCS-GNU: [[AP_NEXT:%.*]] = getelementptr inbounds i8, i8* [[AP]], i32 16<br class="">
// APCS-GNU: [[AP_CAST:%.*]] = bitcast i8* [[AP]] to <5 x i16>*<br class="">
<br class="">
Modified: cfe/trunk/test/CodeGen/arm-neon-misc.c<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-neon-misc.c?rev=304201&r1=304200&r2=304201&view=diff" class="">
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-neon-misc.c?rev=304201&r1=304200&r2=304201&view=diff</a><br class="">
==============================================================================<br class="">
--- cfe/trunk/test/CodeGen/arm-neon-misc.c (original)<br class="">
+++ cfe/trunk/test/CodeGen/arm-neon-misc.c Tue May 30 05:12:15 2017<br class="">
@@ -32,3 +32,11 @@ void t2(uint64_t *src1, uint8_t *src2, u<br class="">
*dst = q;<br class="">
// CHECK: store <2 x i64><br class="">
}<br class="">
+<br class="">
+// Neon types have 64-bit alignment<br class="">
+int32x4_t gl_b;<br class="">
+void t3(int32x4_t *src) {<br class="">
+// CHECK: @t3<br class="">
+ gl_b = *src;<br class="">
+// CHECK: store <4 x i32> {{%.*}}, <4 x i32>* @gl_b, align 8<br class="">
+}<br class="">
<br class="">
Modified: cfe/trunk/test/CodeGen/arm-swiftcall.c<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-swiftcall.c?rev=304201&r1=304200&r2=304201&view=diff" class="">
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-swiftcall.c?rev=304201&r1=304200&r2=304201&view=diff</a><br class="">
==============================================================================<br class="">
--- cfe/trunk/test/CodeGen/arm-swiftcall.c (original)<br class="">
+++ cfe/trunk/test/CodeGen/arm-swiftcall.c Tue May 30 05:12:15 2017<br class="">
@@ -343,7 +343,7 @@ typedef union {<br class="">
} union_hom_fp_partial;<br class="">
TEST(union_hom_fp_partial)<br class="">
// CHECK-LABEL: define void @test_union_hom_fp_partial()<br class="">
-// CHECK: [[TMP:%.*]] = alloca [[REC:%.*]], align 16<br class="">
+// CHECK: [[TMP:%.*]] = alloca [[REC:%.*]], align 8<br class="">
// CHECK: [[CALL:%.*]] = call [[SWIFTCC]] [[UAGG:{ float, float, float, float }]] @return_union_hom_fp_partial()<br class="">
// CHECK: [[CAST_TMP:%.*]] = bitcast [[REC]]* [[TMP]] to [[AGG:{ float, float, float, float }]]*<br class="">
// CHECK: [[T0:%.*]] = getelementptr inbounds [[AGG]], [[AGG]]* [[CAST_TMP]], i32 0, i32 0<br class="">
@@ -376,7 +376,7 @@ typedef union {<br class="">
} union_het_fpv_partial;<br class="">
TEST(union_het_fpv_partial)<br class="">
// CHECK-LABEL: define void @test_union_het_fpv_partial()<br class="">
-// CHECK: [[TMP:%.*]] = alloca [[REC:%.*]], align 16<br class="">
+// CHECK: [[TMP:%.*]] = alloca [[REC:%.*]], align 8<br class="">
// CHECK: [[CALL:%.*]] = call [[SWIFTCC]] [[UAGG:{ i32, i32, float, float }]] @return_union_het_fpv_partial()<br class="">
// CHECK: [[CAST_TMP:%.*]] = bitcast [[REC]]* [[TMP]] to [[AGG:{ i32, i32, float, float }]]*<br class="">
// CHECK: [[T0:%.*]] = getelementptr inbounds [[AGG]], [[AGG]]* [[CAST_TMP]], i32 0, i32 0<br class="">
@@ -413,7 +413,7 @@ TEST(int4)<br class="">
<br class="">
TEST(int8)<br class="">
// CHECK-LABEL: define {{.*}} @return_int8()<br class="">
-// CHECK: [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32<br class="">
+// CHECK: [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 8<br class="">
// CHECK: [[VAR:%.*]] = alloca [[REC]], align<br class="">
// CHECK: store<br class="">
// CHECK: load<br class="">
@@ -457,7 +457,7 @@ TEST(int8)<br class="">
<br class="">
TEST(int5)<br class="">
// CHECK-LABEL: define {{.*}} @return_int5()<br class="">
-// CHECK: [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32<br class="">
+// CHECK: [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 8<br class="">
// CHECK: [[VAR:%.*]] = alloca [[REC]], align<br class="">
// CHECK: store<br class="">
// CHECK: load<br class="">
<br class="">
Modified: cfe/trunk/test/CodeGen/armv7k-abi.c<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/armv7k-abi.c?rev=304201&r1=304200&r2=304201&view=diff" class="">
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/armv7k-abi.c?rev=304201&r1=304200&r2=304201&view=diff</a><br class="">
==============================================================================<br class="">
--- cfe/trunk/test/CodeGen/armv7k-abi.c (original)<br class="">
+++ cfe/trunk/test/CodeGen/armv7k-abi.c Tue May 30 05:12:15 2017<br class="">
@@ -83,11 +83,11 @@ typedef struct {<br class="">
OddlySizedStruct return_oddly_sized_struct() {}<br class="">
<br class="">
// CHECK: define <4 x float> @test_va_arg_vec(i8* %l)<br class="">
-// CHECK: [[ALIGN_TMP:%.*]] = add i32 {{%.*}}, 15<br class="">
-// CHECK: [[ALIGNED:%.*]] = and i32 [[ALIGN_TMP]], -16<br class="">
+// CHECK: [[ALIGN_TMP:%.*]] = add i32 {{%.*}}, 7<br class="">
+// CHECK: [[ALIGNED:%.*]] = and i32 [[ALIGN_TMP]], -8<br class="">
// CHECK: [[ALIGNED_I8:%.*]] = inttoptr i32 [[ALIGNED]] to i8*<br class="">
// CHECK: [[ALIGNED_VEC:%.*]] = bitcast i8* [[ALIGNED_I8]] to <4 x float><br class="">
-// CHECK: load <4 x float>, <4 x float>* [[ALIGNED_VEC]], align 16<br class="">
+// CHECK: load <4 x float>, <4 x float>* [[ALIGNED_VEC]], align 8<br class="">
float32x4_t test_va_arg_vec(__builtin_va_list l) {<br class="">
return __builtin_va_arg(l, float32x4_t);<br class="">
}<br class="">
<br class="">
<br class="">
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