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<div dir="ltr" >Sorry about that I've removed the 2 tests causing the issue for now.</div>
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<div dir="ltr" >Sean</div>
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<blockquote data-history-content-modified="1" dir="ltr" style="border-left:solid #aaaaaa 2px; margin-left:5px; padding-left:5px; direction:ltr; margin-right:0px" >----- Original message -----<br>From: Evgenii Stepanov <eugeni.stepanov@gmail.com><br>To: Sean Fertile/Toronto/IBM@IBMCA<br>Cc: cfe-commits <cfe-commits@lists.llvm.org><br>Subject: Re: r291179 - Add vec_insert4b and vec_extract4b functions to altivec.h<br>Date: Thu, Jan 5, 2017 5:16 PM<br>
<div><font size="2" face="Default Monospace,Courier New,Courier,monospace" >Tests on linux/x86_64 are failing with:<br>fatal error: error in backend: Cannot select: intrinsic %llvm.ppc.vsx.xxinsertw<br><br>On Thu, Jan 5, 2017 at 1:43 PM, Sean Fertile via cfe-commits<br><cfe-commits@lists.llvm.org> wrote:<br>> Author: sfertile<br>> Date: Thu Jan 5 15:43:30 2017<br>> New Revision: 291179<br>><br>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=291179&view=rev" target="_blank" >http://llvm.org/viewvc/llvm-project?rev=291179&view=rev</a><br>> Log:<br>> Add vec_insert4b and vec_extract4b functions to altivec.h<br>><br>> Add builtins for the functions and custom codegen mapping the builtins to their<br>> corresponding intrinsics and handling the endian related swapping.<br>><br>> <a href="https://reviews.llvm.org/D26546" target="_blank" >https://reviews.llvm.org/D26546</a><br>><br>> Added:<br>> cfe/trunk/test/CodeGen/builtins-ppc-error.c<br>> cfe/trunk/test/CodeGen/builtins-ppc-extractword-error.c<br>> cfe/trunk/test/CodeGen/builtins-ppc-insertword-error.c<br>> Modified:<br>> cfe/trunk/include/clang/Basic/BuiltinsPPC.def<br>> cfe/trunk/lib/CodeGen/CGBuiltin.cpp<br>> cfe/trunk/lib/Headers/altivec.h<br>> cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c<br>><br>> Modified: cfe/trunk/include/clang/Basic/BuiltinsPPC.def<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=291179&r1=291178&r2=291179&view=diff" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsPPC.def?rev=291179&r1=291178&r2=291179&view=diff</a><br>> ==============================================================================<br>> --- cfe/trunk/include/clang/Basic/BuiltinsPPC.def (original)<br>> +++ cfe/trunk/include/clang/Basic/BuiltinsPPC.def Thu Jan 5 15:43:30 2017<br>> @@ -417,6 +417,9 @@ BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us<br>> BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "")<br>> BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "")<br>><br>> +BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "")<br>> +BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")<br>> +<br>> // HTM builtins<br>> BUILTIN(__builtin_tbegin, "UiUIi", "")<br>> BUILTIN(__builtin_tend, "UiUIi", "")<br>><br>> Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=291179&r1=291178&r2=291179&view=diff" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=291179&r1=291178&r2=291179&view=diff</a><br>> ==============================================================================<br>> --- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)<br>> +++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Thu Jan 5 15:43:30 2017<br>> @@ -35,6 +35,11 @@ using namespace clang;<br>> using namespace CodeGen;<br>> using namespace llvm;<br>><br>> +static<br>> +int64_t clamp(int64_t Value, int64_t Low, int64_t High) {<br>> + return std::min(High, std::max(Low, Value));<br>> +}<br>> +<br>> /// getBuiltinLibFunction - Given a builtin id for a function like<br>> /// "__builtin_fabsf", return a Function* for "fabsf".<br>> llvm::Constant *CodeGenModule::getBuiltinLibFunction(const FunctionDecl *FD,<br>> @@ -8191,6 +8196,85 @@ Value *CodeGenFunction::EmitPPCBuiltinEx<br>> llvm_unreachable("Unknown FMA operation");<br>> return nullptr; // Suppress no-return warning<br>> }<br>> +<br>> + case PPC::BI__builtin_vsx_insertword: {<br>> + llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_vsx_xxinsertw);<br>> +<br>> + // Third argument is a compile time constant int. It must be clamped to<br>> + // to the range [0, 12].<br>> + ConstantInt *ArgCI = dyn_cast<ConstantInt>(Ops[2]);<br>> + assert(ArgCI &&<br>> + "Third arg to xxinsertw intrinsic must be constant integer");<br>> + const int64_t MaxIndex = 12;<br>> + int64_t Index = clamp(ArgCI->getSExtValue(), 0, MaxIndex);<br>> +<br>> + // The builtin semantics don't exactly match the xxinsertw instructions<br>> + // semantics (which ppc_vsx_xxinsertw follows). The builtin extracts the<br>> + // word from the first argument, and inserts it in the second argument. The<br>> + // instruction extracts the word from its second input register and inserts<br>> + // it into its first input register, so swap the first and second arguments.<br>> + std::swap(Ops[0], Ops[1]);<br>> +<br>> + // Need to cast the second argument from a vector of unsigned int to a<br>> + // vector of long long.<br>> + Ops[1] = Builder.CreateBitCast(Ops[1], llvm::VectorType::get(Int64Ty, 2));<br>> +<br>> + if (getTarget().isLittleEndian()) {<br>> + // Create a shuffle mask of (1, 0)<br>> + Constant *ShuffleElts[2] = { ConstantInt::get(Int32Ty, 1),<br>> + ConstantInt::get(Int32Ty, 0)<br>> + };<br>> + Constant *ShuffleMask = llvm::ConstantVector::get(ShuffleElts);<br>> +<br>> + // Reverse the double words in the vector we will extract from.<br>> + Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int64Ty, 2));<br>> + Ops[0] = Builder.CreateShuffleVector(Ops[0], Ops[0], ShuffleMask);<br>> +<br>> + // Reverse the index.<br>> + Index = MaxIndex - Index;<br>> + }<br>> +<br>> + // Intrinsic expects the first arg to be a vector of int.<br>> + Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int32Ty, 4));<br>> + Ops[2] = ConstantInt::getSigned(Int32Ty, Index);<br>> + return Builder.CreateCall(F, Ops);<br>> + }<br>> +<br>> + case PPC::BI__builtin_vsx_extractuword: {<br>> + llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_vsx_xxextractuw);<br>> +<br>> + // Intrinsic expects the first argument to be a vector of doublewords.<br>> + Ops[0] = Builder.CreateBitCast(Ops[0], llvm::VectorType::get(Int64Ty, 2));<br>> +<br>> + // The second argument is a compile time constant int that needs to<br>> + // be clamped to the range [0, 12].<br>> + ConstantInt *ArgCI = dyn_cast<ConstantInt>(Ops[1]);<br>> + assert(ArgCI &&<br>> + "Second Arg to xxextractuw intrinsic must be a constant integer!");<br>> + const int64_t MaxIndex = 12;<br>> + int64_t Index = clamp(ArgCI->getSExtValue(), 0, MaxIndex);<br>> +<br>> + if (getTarget().isLittleEndian()) {<br>> + // Reverse the index.<br>> + Index = MaxIndex - Index;<br>> + Ops[1] = ConstantInt::getSigned(Int32Ty, Index);<br>> +<br>> + // Emit the call, then reverse the double words of the results vector.<br>> + Value *Call = Builder.CreateCall(F, Ops);<br>> +<br>> + // Create a shuffle mask of (1, 0)<br>> + Constant *ShuffleElts[2] = { ConstantInt::get(Int32Ty, 1),<br>> + ConstantInt::get(Int32Ty, 0)<br>> + };<br>> + Constant *ShuffleMask = llvm::ConstantVector::get(ShuffleElts);<br>> +<br>> + Value *ShuffleCall = Builder.CreateShuffleVector(Call, Call, ShuffleMask);<br>> + return ShuffleCall;<br>> + } else {<br>> + Ops[1] = ConstantInt::getSigned(Int32Ty, Index);<br>> + return Builder.CreateCall(F, Ops);<br>> + }<br>> + }<br>> }<br>> }<br>><br>><br>> Modified: cfe/trunk/lib/Headers/altivec.h<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=291179&r1=291178&r2=291179&view=diff" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/altivec.h?rev=291179&r1=291178&r2=291179&view=diff</a><br>> ==============================================================================<br>> --- cfe/trunk/lib/Headers/altivec.h (original)<br>> +++ cfe/trunk/lib/Headers/altivec.h Thu Jan 5 15:43:30 2017<br>> @@ -12574,6 +12574,9 @@ static __inline__ float __ATTRS_o_ai vec<br>><br>> #ifdef __POWER9_VECTOR__<br>><br>> +#define vec_insert4b __builtin_vsx_insertword<br>> +#define vec_extract4b __builtin_vsx_extractuword<br>> +<br>> /* vec_extract_exp */<br>><br>> static __inline__ vector unsigned int __ATTRS_o_ai<br>><br>> Added: cfe/trunk/test/CodeGen/builtins-ppc-error.c<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-error.c?rev=291179&view=auto" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-error.c?rev=291179&view=auto</a><br>> ==============================================================================<br>> --- cfe/trunk/test/CodeGen/builtins-ppc-error.c (added)<br>> +++ cfe/trunk/test/CodeGen/builtins-ppc-error.c Thu Jan 5 15:43:30 2017<br>> @@ -0,0 +1,20 @@<br>> +// REQUIRES: powerpc-registered-target<br>> +<br>> +// RUN: %clang_cc1 -faltivec -target-feature +power9-vector \<br>> +// RUN: -triple powerpc64-unknown-unknown -fsyntax-only \<br>> +// RUN: -Wall -Werror -verify %s<br>> +<br>> +// RUN: %clang_cc1 -faltivec -target-feature +power9-vector \<br>> +// RUN: -triple powerpc64le-unknown-unknown -fsyntax-only \<br>> +// RUN: -Wall -Werror -verify %s<br>> +<br>> +#include <altivec.h><br>> +<br>> +extern vector signed int vsi;<br>> +extern vector unsigned char vuc;<br>> +<br>> +void testInsertWord1(void) {<br>> + int index = 5;<br>> + vector unsigned char v1 = vec_insert4b(vsi, vuc, index); // expected-error {{argument to '__builtin_vsx_insertword' must be a constant integer}}<br>> + vector unsigned long long v2 = vec_extract4b(vuc, index); // expected-error {{argument to '__builtin_vsx_extractuword' must be a constant integer}}<br>> +}<br>><br>> Added: cfe/trunk/test/CodeGen/builtins-ppc-extractword-error.c<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-extractword-error.c?rev=291179&view=auto" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-extractword-error.c?rev=291179&view=auto</a><br>> ==============================================================================<br>> --- cfe/trunk/test/CodeGen/builtins-ppc-extractword-error.c (added)<br>> +++ cfe/trunk/test/CodeGen/builtins-ppc-extractword-error.c Thu Jan 5 15:43:30 2017<br>> @@ -0,0 +1,15 @@<br>> +// REQUIRES: powerpc-registered-target<br>> +// XFAIL: powerpc<br>> +<br>> +// RUN: %clang -faltivec -target powerpc64le-unknown-unknown -mcpu=power8 \<br>> +// RUN: -Wall -Wextra -c %s<br>> +// RUN: %clang -faltivec -target powerpc64-unknown-unknown -mcpu=power8 \<br>> +// RUN: -Wall -Wextra -c %s<br>> +<br>> +// Expect the compile to fail with "cannot compile this builtin function yet"<br>> +extern vector signed int vsi;<br>> +extern vector unsigned char vuc;<br>> +<br>> +vector unsigned long long testExtractWord(void) {<br>> + return __builtin_vsx_extractuword(vuc, 12);<br>> +}<br>><br>> Added: cfe/trunk/test/CodeGen/builtins-ppc-insertword-error.c<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-insertword-error.c?rev=291179&view=auto" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-insertword-error.c?rev=291179&view=auto</a><br>> ==============================================================================<br>> --- cfe/trunk/test/CodeGen/builtins-ppc-insertword-error.c (added)<br>> +++ cfe/trunk/test/CodeGen/builtins-ppc-insertword-error.c Thu Jan 5 15:43:30 2017<br>> @@ -0,0 +1,16 @@<br>> +// REQUIRES: powerpc-registered-target<br>> +// XFAIL: powerpc<br>> +<br>> +// RUN: %clang -faltivec -target powerpc64le-unknown-unknown -mcpu=power8 \<br>> +// RUN: -Wall -Werror -c %s<br>> +<br>> +// RUN: %clang -faltivec -target powerpc64-unknown-unknown -mcpu=power8 \<br>> +// RUN: -Wall -Werror -c %s<br>> +<br>> +// expect to fail with diagnostic: "cannot compile this builtin function yet"<br>> +extern vector signed int vsi;<br>> +extern vector unsigned char vuc;<br>> +<br>> +vector unsigned char testInsertWord(void) {<br>> + return __builtin_vsx_insertword(vsi, vuc, 0);<br>> +}<br>><br>> Modified: cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c<br>> URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c?rev=291179&r1=291178&r2=291179&view=diff" target="_blank" >http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c?rev=291179&r1=291178&r2=291179&view=diff</a><br>> ==============================================================================<br>> --- cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c (original)<br>> +++ cfe/trunk/test/CodeGen/builtins-ppc-p9vector.c Thu Jan 5 15:43:30 2017<br>> @@ -1166,17 +1166,52 @@ vector float test114(void) {<br>> // CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3><br>> // CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})<br>> // CHECK-BE-NEXT: ret <4 x float><br>> -// CHECK-LE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef><br>> -// CHECK-LE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})<br>> -// CHECK-LE-NEXT: ret <4 x float><br>> +// CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef><br>> +// CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})<br>> +// CHECK-NEXT: ret <4 x float><br>> return vec_extract_fp32_from_shorth(vusa);<br>> }<br>> vector float test115(void) {<br>> // CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7><br>> // CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})<br>> // CHECK-BE-NEXT: ret <4 x float><br>> -// CHECK-LE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef><br>> -// CHECK-LE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})<br>> -// CHECK-LE-NEXT: ret <4 x float><br>> +// CHECK: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef><br>> +// CHECK: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}})<br>> +// CHECK-NEXT: ret <4 x float><br>> return vec_extract_fp32_from_shortl(vusa);<br>> }<br>> +vector unsigned char test116(void) {<br>> +// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 7)<br>> +// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8><br>> +// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0><br>> +// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32><br>> +// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 5)<br>> +// CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8><br>> + return vec_insert4b(vuia, vuca, 7);<br>> +}<br>> +vector unsigned char test117(void) {<br>> +// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <2 x i64> {{.+}}, i32 12)<br>> +// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8><br>> +// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0><br>> +// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32><br>> +// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 0)<br>> +// CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8><br>> + return vec_insert4b(vuia, vuca, 13);<br>> +}<br>> +vector unsigned long long test118(void) {<br>> +// CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 11)<br>> +// CHECK-BE-NEXT: ret <2 x i64><br>> +// CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 1)<br>> +// CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0><br>> +// CHECK-NEXT: ret <2 x i64><br>> + return vec_extract4b(vuca, 11);<br>> +}<br>> +vector unsigned long long test119(void) {<br>> +// CHECK-BE: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 0)<br>> +// CHECK-BE-NEXT: ret <2 x i64><br>> +// CHECK: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> {{.+}}, i32 12)<br>> +// CHECK-NEXT: shufflevector <2 x i64> [[T1]], <2 x i64> [[T1]], <2 x i32> <i32 1, i32 0><br>> +// CHECK-NEXT: ret <2 x i64><br>> + return vec_extract4b(vuca, -5);<br>> +}<br>> +<br>><br>><br>> _______________________________________________<br>> cfe-commits mailing list<br>> cfe-commits@lists.llvm.org<br>> <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits" target="_blank" >http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits</a></font><br> </div></blockquote>
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