<div dir="ltr">Hi Eric,<div><br></div><div>While I agree with you in principle, Alexandros has just pointed out to me that all the other NEON intrinsics have such -O3 tests, and thinking about it I do think they add value. They test the full-trip through the compiler and ensure that Clang and LLVM have matching ideas of the IR interface exposed by the intrinsics.</div><div><br></div><div>AIUI, Alexandros wrote LLVM backend tests in addition to these. It does look like there are no tests just checking Clang's IR output - I think these should indeed be written.</div><div><br></div><div>In summary, I agree with you that we need tests for both Clang and LLVM separately. However I also think the full-trip tests add significant value and wouldn't like to see them removed, and there's significant prior art in this area so if we did decide they needed to be gone, we'd need a good discussion on how to regain the testing coverage we'd lose.</div><div><br></div><div>Cheers,</div><div><br></div><div>James</div></div><br><div class="gmail_quote"><div dir="ltr">On Sun, 29 Nov 2015 at 20:40 Eric Christopher via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org">cfe-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><p dir="ltr">Hi,</p>
<p dir="ltr">This is entirely the wrong way to do these tests. They shouldn't depend on assembly output or optimization. Please split them onto frontend IR tests and backend assembly tests. </p>
<p dir="ltr">Thanks!</p>
<br><div class="gmail_quote"><div dir="ltr">On Sun, Nov 29, 2015, 2:56 AM Alexandros Lamprineas via cfe-commits <<a href="mailto:cfe-commits@lists.llvm.org" target="_blank">cfe-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: alelab01<br>
Date: Sun Nov 29 04:53:28 2015<br>
New Revision: 254251<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=254251&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=254251&view=rev</a><br>
Log:<br>
ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply<br>
Add/Subtract.<br>
<br>
Add missing tests that accidentally were not committed in rL254250.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D14982" rel="noreferrer" target="_blank">http://reviews.llvm.org/D14982</a><br>
<br>
Added:<br>
cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c<br>
cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c<br>
<br>
Added: cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c?rev=254251&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c?rev=254251&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c (added)<br>
+++ cfe/trunk/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c Sun Nov 29 04:53:28 2015<br>
@@ -0,0 +1,128 @@<br>
+// REQUIRES: aarch64-registered-target<br>
+<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \<br>
+// RUN: -target-feature +v8.1a -O3 -S -o - %s \<br>
+// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64<br>
+<br>
+ #include <arm_neon.h><br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s16<br>
+int16x4_t test_vqrdmlah_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]<br>
+ return vqrdmlah_laneq_s16(a, b, v, 7);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlah_laneq_s32<br>
+int32x2_t test_vqrdmlah_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]<br>
+ return vqrdmlah_laneq_s32(a, b, v, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s16<br>
+int16x8_t test_vqrdmlahq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) {<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]<br>
+ return vqrdmlahq_laneq_s16(a, b, v, 7);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahq_laneq_s32<br>
+int32x4_t test_vqrdmlahq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) {<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]<br>
+ return vqrdmlahq_laneq_s32(a, b, v, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahh_s16<br>
+int16_t test_vqrdmlahh_s16(int16_t a, int16_t b, int16_t c) {<br>
+// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}<br>
+ return vqrdmlahh_s16(a, b, c);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahs_s32<br>
+int32_t test_vqrdmlahs_s32(int32_t a, int32_t b, int32_t c) {<br>
+// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}<br>
+ return vqrdmlahs_s32(a, b, c);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahh_lane_s16<br>
+int16_t test_vqrdmlahh_lane_s16(int16_t a, int16_t b, int16x4_t c) {<br>
+// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3]<br>
+ return vqrdmlahh_lane_s16(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahs_lane_s32<br>
+int32_t test_vqrdmlahs_lane_s32(int32_t a, int32_t b, int32x2_t c) {<br>
+// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]<br>
+ return vqrdmlahs_lane_s32(a, b, c, 1);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahh_laneq_s16<br>
+int16_t test_vqrdmlahh_laneq_s16(int16_t a, int16_t b, int16x8_t c) {<br>
+// CHECK-AARCH64: sqrdmlah {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7]<br>
+ return vqrdmlahh_laneq_s16(a, b, c, 7);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlahs_laneq_s32<br>
+int32_t test_vqrdmlahs_laneq_s32(int32_t a, int32_t b, int32x4_t c) {<br>
+// CHECK-AARCH64: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]<br>
+ return vqrdmlahs_laneq_s32(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlsh_laneq_s16<br>
+int16x4_t test_vqrdmlsh_laneq_s16(int16x4_t a, int16x4_t b, int16x8_t v) {<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[7]<br>
+ return vqrdmlsh_laneq_s16(a, b, v, 7);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlsh_laneq_s32<br>
+int32x2_t test_vqrdmlsh_laneq_s32(int32x2_t a, int32x2_t b, int32x4_t v) {<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[3]<br>
+ return vqrdmlsh_laneq_s32(a, b, v, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshq_laneq_s16<br>
+int16x8_t test_vqrdmlshq_laneq_s16(int16x8_t a, int16x8_t b, int16x8_t v) {<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[7]<br>
+ return vqrdmlshq_laneq_s16(a, b, v, 7);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshq_laneq_s32<br>
+int32x4_t test_vqrdmlshq_laneq_s32(int32x4_t a, int32x4_t b, int32x4_t v) {<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[3]<br>
+ return vqrdmlshq_laneq_s32(a, b, v, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshh_s16<br>
+int16_t test_vqrdmlshh_s16(int16_t a, int16_t b, int16_t c) {<br>
+// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}<br>
+ return vqrdmlshh_s16(a, b, c);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshs_s32<br>
+int32_t test_vqrdmlshs_s32(int32_t a, int32_t b, int32_t c) {<br>
+// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}<br>
+ return vqrdmlshs_s32(a, b, c);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshh_lane_s16<br>
+int16_t test_vqrdmlshh_lane_s16(int16_t a, int16_t b, int16x4_t c) {<br>
+// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[3]<br>
+ return vqrdmlshh_lane_s16(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshs_lane_s32<br>
+int32_t test_vqrdmlshs_lane_s32(int32_t a, int32_t b, int32x2_t c) {<br>
+// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]<br>
+ return vqrdmlshs_lane_s32(a, b, c, 1);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshh_laneq_s16<br>
+int16_t test_vqrdmlshh_laneq_s16(int16_t a, int16_t b, int16x8_t c) {<br>
+// CHECK-AARCH64: sqrdmlsh {{h[0-9]+|v[0-9]+.4h}}, {{h[0-9]+|v[0-9]+.4h}}, {{v[0-9]+}}.h[7]<br>
+ return vqrdmlshh_laneq_s16(a, b, c, 7);<br>
+}<br>
+<br>
+// CHECK-AARCH64-LABEL: test_vqrdmlshs_laneq_s32<br>
+int32_t test_vqrdmlshs_laneq_s32(int32_t a, int32_t b, int32x4_t c) {<br>
+// CHECK-AARCH64: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]<br>
+ return vqrdmlshs_laneq_s32(a, b, c, 3);<br>
+}<br>
+<br>
<br>
Added: cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c?rev=254251&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c?rev=254251&view=auto</a><br>
==============================================================================<br>
--- cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c (added)<br>
+++ cfe/trunk/test/CodeGen/arm-v8.1a-neon-intrinsics.c Sun Nov 29 04:53:28 2015<br>
@@ -0,0 +1,121 @@<br>
+// RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \<br>
+// RUN: -O3 -S -o - %s \<br>
+// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM<br>
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \<br>
+// RUN: -target-feature +v8.1a -O3 -S -o - %s \<br>
+// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64<br>
+<br>
+#include <arm_neon.h><br>
+<br>
+// CHECK-LABEL: test_vqrdmlah_s16<br>
+int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) {<br>
+// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h<br>
+ return vqrdmlah_s16(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlah_s32<br>
+int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) {<br>
+// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s<br>
+ return vqrdmlah_s32(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlahq_s16<br>
+int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {<br>
+// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h<br>
+ return vqrdmlahq_s16(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlahq_s32<br>
+int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {<br>
+// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s<br>
+ return vqrdmlahq_s32(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlah_lane_s16<br>
+int16x4_t test_vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {<br>
+// CHECK-ARM: vqrdmlah.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3]<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]<br>
+ return vqrdmlah_lane_s16(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlah_lane_s32<br>
+int32x2_t test_vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {<br>
+// CHECK-ARM: vqrdmlah.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1]<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]<br>
+ return vqrdmlah_lane_s32(a, b, c, 1);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlahq_lane_s16<br>
+int16x8_t test_vqrdmlahq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {<br>
+// CHECK-ARM: vqrdmlah.s16 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[3]<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]<br>
+ return vqrdmlahq_lane_s16(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlahq_lane_s32<br>
+int32x4_t test_vqrdmlahq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {<br>
+// CHECK-ARM: vqrdmlah.s32 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[1]<br>
+// CHECK-AARCH64: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]<br>
+ return vqrdmlahq_lane_s32(a, b, c, 1);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlsh_s16<br>
+int16x4_t test_vqrdmlsh_s16(int16x4_t a, int16x4_t b, int16x4_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h<br>
+ return vqrdmlsh_s16(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlsh_s32<br>
+int32x2_t test_vqrdmlsh_s32(int32x2_t a, int32x2_t b, int32x2_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s<br>
+ return vqrdmlsh_s32(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlshq_s16<br>
+int16x8_t test_vqrdmlshq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s16 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h<br>
+ return vqrdmlshq_s16(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlshq_s32<br>
+int32x4_t test_vqrdmlshq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s<br>
+ return vqrdmlshq_s32(a, b, c);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlsh_lane_s16<br>
+int16x4_t test_vqrdmlsh_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s16 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[3]<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.h[3]<br>
+ return vqrdmlsh_lane_s16(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlsh_lane_s32<br>
+int32x2_t test_vqrdmlsh_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}[1]<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]<br>
+ return vqrdmlsh_lane_s32(a, b, c, 1);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlshq_lane_s16<br>
+int16x8_t test_vqrdmlshq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s16 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[3]<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.h[3]<br>
+ return vqrdmlshq_lane_s16(a, b, c, 3);<br>
+}<br>
+<br>
+// CHECK-LABEL: test_vqrdmlshq_lane_s32<br>
+int32x4_t test_vqrdmlshq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {<br>
+// CHECK-ARM: vqrdmlsh.s32 q{{[0-9]+}}, q{{[0-9]+}}, d{{[0-9]+}}[1]<br>
+// CHECK-AARCH64: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]<br>
+ return vqrdmlshq_lane_s32(a, b, c, 1);<br>
+}<br>
+<br>
<br>
<br>
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