<div dir="ltr">Committed as r196362.<br></div><div class="gmail_extra"><br><br><div class="gmail_quote">2013/12/3 Kevin Qin <span dir="ltr"><<a href="mailto:kevinqindev@gmail.com" target="_blank">kevinqindev@gmail.com</a>></span><br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">kevin.qin added you to the CC list for the revision "[AArch64 NEON] Implement intrinsic vceqz_f64 -llvm".<br>
<div class="HOEnZb"><div class="h5"><br>
Hi,<br>
Please review, thanks.<br>
<br>
<a href="http://llvm-reviews.chandlerc.com/D2314" target="_blank">http://llvm-reviews.chandlerc.com/D2314</a><br>
<br>
Files:<br>
lib/Target/AArch64/AArch64InstrNEON.td<br>
test/CodeGen/AArch64/neon-scalar-fp-compare.ll<br>
<br>
Index: lib/Target/AArch64/AArch64InstrNEON.td<br>
===================================================================<br>
--- lib/Target/AArch64/AArch64InstrNEON.td<br>
+++ lib/Target/AArch64/AArch64InstrNEON.td<br>
@@ -4323,7 +4323,7 @@<br>
[],<br>
NoItinerary>;<br>
def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,<br>
- (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),<br>
+ (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),<br>
!strconcat(asmop, "\t$Rd, $Rn, $FPImm"),<br>
[],<br>
NoItinerary>;<br>
@@ -4339,11 +4339,11 @@<br>
Instruction INSTS,<br>
Instruction INSTD> {<br>
def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),<br>
- (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),<br>
- (INSTS FPR32:$Rn, fpimm:$FPImm)>;<br>
+ (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),<br>
+ (INSTS FPR32:$Rn, fpz32:$FPImm)>;<br>
def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),<br>
- (v1f64 (bitconvert (v8i8 Neon_AllZero))))),<br>
- (INSTD FPR64:$Rn, 0)>;<br>
+ (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),<br>
+ (INSTD FPR64:$Rn, fpz32:$FPImm)>;<br>
}<br>
<br>
multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,<br>
@@ -5046,6 +5046,8 @@<br>
defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;<br>
defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,<br>
FCMEQZssi, FCMEQZddi>;<br>
+def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),<br>
+ (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;<br>
<br>
// Scalar Floating-point Compare Mask Greater Than Or Equal<br>
defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;<br>
Index: test/CodeGen/AArch64/neon-scalar-fp-compare.ll<br>
===================================================================<br>
--- test/CodeGen/AArch64/neon-scalar-fp-compare.ll<br>
+++ test/CodeGen/AArch64/neon-scalar-fp-compare.ll<br>
@@ -24,6 +24,15 @@<br>
ret i64 %0<br>
}<br>
<br>
+define <1 x i64> @test_vceqz_f64(<1 x double> %a) #0 {<br>
+; CHECK: test_vceqz_f64<br>
+; CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0.0<br>
+entry:<br>
+ %0 = fcmp oeq <1 x double> %a, zeroinitializer<br>
+ %vceqz.i = zext <1 x i1> %0 to <1 x i64><br>
+ ret <1 x i64> %vceqz.i<br>
+}<br>
+<br>
define i32 @test_vceqzs_f32(float %a) {<br>
; CHECK: test_vceqzs_f32<br>
; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0<br>
@@ -39,7 +48,7 @@<br>
; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0<br>
entry:<br>
%vceq.i = insertelement <1 x double> undef, double %a, i32 0<br>
- %vceq1.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double> %vceq.i, <1 x double> zeroinitializer)<br>
+ %vceq1.i = tail call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double> %vceq.i, <1 x float> zeroinitializer) #5<br>
%0 = extractelement <1 x i64> %vceq1.i, i32 0<br>
ret i64 %0<br>
}<br>
@@ -81,7 +90,7 @@<br>
; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0<br>
entry:<br>
%vcge.i = insertelement <1 x double> undef, double %a, i32 0<br>
- %vcge1.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> zeroinitializer)<br>
+ %vcge1.i = tail call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double> %vcge.i, <1 x float> zeroinitializer) #5<br>
%0 = extractelement <1 x i64> %vcge1.i, i32 0<br>
ret i64 %0<br>
}<br>
@@ -123,7 +132,7 @@<br>
; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0<br>
entry:<br>
%vcgt.i = insertelement <1 x double> undef, double %a, i32 0<br>
- %vcgt1.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> zeroinitializer)<br>
+ %vcgt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double> %vcgt.i, <1 x float> zeroinitializer) #5<br>
%0 = extractelement <1 x i64> %vcgt1.i, i32 0<br>
ret i64 %0<br>
}<br>
@@ -165,7 +174,7 @@<br>
; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0<br>
entry:<br>
%vcle.i = insertelement <1 x double> undef, double %a, i32 0<br>
- %vcle1.i = call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f64(<1 x double> %vcle.i, <1 x double> zeroinitializer)<br>
+ %vcle1.i = tail call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double> %vcle.i, <1 x float> zeroinitializer) #5<br>
%0 = extractelement <1 x i64> %vcle1.i, i32 0<br>
ret i64 %0<br>
}<br>
@@ -207,7 +216,7 @@<br>
; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0<br>
entry:<br>
%vclt.i = insertelement <1 x double> undef, double %a, i32 0<br>
- %vclt1.i = call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f64(<1 x double> %vclt.i, <1 x double> zeroinitializer)<br>
+ %vclt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double> %vclt.i, <1 x float> zeroinitializer) #5<br>
%0 = extractelement <1 x i64> %vclt1.i, i32 0<br>
ret i64 %0<br>
}<br>
@@ -301,15 +310,18 @@<br>
}<br>
<br>
declare <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
+declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)<br>
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)<br>
declare <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
+declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)<br>
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)<br>
declare <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
-declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)<br>
+declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)<br>
declare <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
+declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)<br>
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)<br>
declare <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
-declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)<br>
+declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)<br>
declare <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)<br>
declare <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)<br>
</div></div><br>_______________________________________________<br>
cfe-commits mailing list<br>
<a href="mailto:cfe-commits@cs.uiuc.edu">cfe-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits</a><br>
<br></blockquote></div><br><br clear="all"><div><br></div>-- <br><div dir="ltr">Best Regards,<div><br></div><div>Kevin Qin</div></div>
</div>