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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Eric,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>To me it would be odd if the AArch64 CLI behaved differently to AArch32, except where absolutely necessary.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>So I think the most important thing is for the two CLIs to be consistent. That doesn't necessarily mean that the AArch32 CLI couldn't change or be extended in the ways you suggest.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Could you elaborate on those 'reasons'? What are the disadvantages of the present approach and/or advantages of your approach?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Bernie<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-left:solid blue 1.5pt;padding:0cm 0cm 0cm 4.0pt'><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> cfe-commits-bounces@cs.uiuc.edu [mailto:cfe-commits-bounces@cs.uiuc.edu] <b>On Behalf Of </b>Eric Christopher<br><b>Sent:</b> 07 November 2013 22:09<br><b>To:</b> Amara Emerson; Nigel Stephens<br><b>Cc:</b> cfe-commits@cs.uiuc.edu<br><b>Subject:</b> Re: r193740 - [AArch64] Add some CPU targets for "generic", A-53 and A-57.<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal style='margin-bottom:12.0pt'><o:p> </o:p></p><div><p class=MsoNormal>On Thu, Nov 7, 2013 at 6:47 AM, Amara Emerson <<a href="mailto:amara.emerson@arm.com" target="_blank">amara.emerson@arm.com</a>> wrote:<o:p></o:p></p><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.5pt;font-family:Consolas'>Hi Eric,</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.5pt;font-family:Consolas'> </span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.5pt;font-family:Consolas'>Some of the main reasons (there may be more I’m overlooking) for using this scheme is consistency with the existing ARM backend for end users. From our perspective, -march should be restricted to actual architectures, and not one specific implementation. A pragmatic addition is that accepting –march=cortex-a53 would be ambiguous, as cortex-a53 will exist in both the ARM and AArch64 backends. Specifying the CPU name alone is not enough to determine the architecture we’re compiling for. We’ve also never used –mtune, and to begin doing so would not bring us any significant benefits. Hope that answers your questions.</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.5pt;font-family:Consolas'> </span><o:p></o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>It seems odd to saddle the ARM64 port with the mistakes of the previous ARM port. That there's going to be a cortex-a53 for arm64 and arm seems irrelevant since, for the general -arch or -target case, you'll be specifying the triple that you're compiling for so whether you're compiling for 64 or 32-bit will be clear on the command line. Unless you have a plan for cpu families ala the old ARM I really don't see a reason to have this and a lot of reasons not to.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>As far as -mtune, the ARM port was actually the only port in gcc that didn't use -mtune and it caused a lot of odd bugs and complaints. I don't see a reason to limit tuning for a particular processor while targeting the architecture of something else.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Nigel: Can you elaborate here a bit more with the uses you see here?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>-eric<o:p></o:p></p></div><div><p class=MsoNormal> <o:p></o:p></p></div><blockquote style='border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm'><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.5pt;font-family:Consolas'>Amara</span><o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><span style='font-size:10.5pt;font-family:Consolas'> </span><o:p></o:p></p><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm'><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'><b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>] </span><o:p></o:p></p><div><p class=MsoNormal><b>Sent:</b> 06 November 2013 16:34<br><b>To:</b> Amara Emerson<br><b>Cc:</b> <a href="mailto:cfe-commits@cs.uiuc.edu" target="_blank">cfe-commits@cs.uiuc.edu</a><o:p></o:p></p></div><p class=MsoNormal><b>Subject:</b> Re: r193740 - [AArch64] Add some CPU targets for "generic", A-53 and A-57.<o:p></o:p></p></div><div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p><p>Ping? Can you answer this?<o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>On Nov 1, 2013 3:04 PM, "Eric Christopher" <<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>> wrote:<o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Out of curiosity this seems to be enshrining for AArch64 the -march/-mcpu stuff from the old 32-bit arm gcc port. Why is this necessary? Why not just -march=cortex-a53 to generate code for a particular architecture and -mtune=cortex-a53 to tune, but not use any cpu specific instructions for a particular architecture? Can you explain what your thoughts are here?<o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>-eric<o:p></o:p></p></div></div><div><p class=MsoNormal style='mso-margin-top-alt:auto;margin-bottom:12.0pt'> <o:p></o:p></p><div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>On Thu, Oct 31, 2013 at 2:32 AM, Amara Emerson <<a href="mailto:amara.emerson@arm.com" target="_blank">amara.emerson@arm.com</a>> wrote:<o:p></o:p></p><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'>Author: aemerson<br>Date: Thu Oct 31 04:32:33 2013<br>New Revision: 193740<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=193740&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=193740&view=rev</a><br>Log:<br>[AArch64] Add some CPU targets for "generic", A-53 and A-57.<br><br>Enables the clang driver to begin targeting specific CPUs. Introduced a<br>"generic" CPU which will ensure that the optional FP feature is enabled<br>by default when it gets to LLVM, without needing any extra arguments.<br>Cortex-A53 and A-57 are also introduced with tests, although backend<br>handling of them does not yet exist.<br><br>Added:<br> cfe/trunk/test/Driver/aarch64-cpus.c<br> cfe/trunk/test/Driver/aarch64-mfpu.c<br>Modified:<br> cfe/trunk/lib/Basic/Targets.cpp<br> cfe/trunk/lib/Driver/Tools.cpp<br> cfe/trunk/lib/Driver/Tools.h<br><br>Modified: cfe/trunk/lib/Basic/Targets.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=193740&r1=193739&r2=193740&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=193740&r1=193739&r2=193740&view=diff</a><br>==============================================================================<br>--- cfe/trunk/lib/Basic/Targets.cpp (original)<br>+++ cfe/trunk/lib/Basic/Targets.cpp Thu Oct 31 04:32:33 2013<br>@@ -3472,6 +3472,13 @@ public:<br> return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);<br> }<br><br>+ virtual bool setCPU(const std::string &Name) {<br>+ return llvm::StringSwitch<bool>(Name)<br>+ .Case("generic", true)<br>+ .Cases("cortex-a53", "cortex-a57", true)<br>+ .Default(false);<br>+ }<br>+<br> virtual bool handleTargetFeatures(std::vector<std::string> &Features,<br> DiagnosticsEngine &Diags) {<br> FPU = FPUMode;<br><br>Modified: cfe/trunk/lib/Driver/Tools.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=193740&r1=193739&r2=193740&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.cpp?rev=193740&r1=193739&r2=193740&view=diff</a><br>==============================================================================<br>--- cfe/trunk/lib/Driver/Tools.cpp (original)<br>+++ cfe/trunk/lib/Driver/Tools.cpp Thu Oct 31 04:32:33 2013<br>@@ -539,6 +539,26 @@ static std::string getARMTargetCPU(const<br> .Default("arm7tdmi");<br> }<br><br>+/// getAArch64TargetCPU - Get the (LLVM) name of the AArch64 cpu we are targeting.<br>+//<br>+// FIXME: tblgen this.<br>+static std::string getAArch64TargetCPU(const ArgList &Args,<br>+ const llvm::Triple &Triple) {<br>+ // FIXME: Warn on inconsistent use of -mcpu and -march.<br>+<br>+ // If we have -mcpu=, use that.<br>+ if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {<br>+ StringRef MCPU = A->getValue();<br>+ // Handle -mcpu=native.<br>+ if (MCPU == "native")<br>+ return llvm::sys::getHostCPUName();<br>+ else<br>+ return MCPU;<br>+ }<br>+<br>+ return "generic";<br>+}<br>+<br> // FIXME: Move to target hook.<br> static bool isSignedCharDefault(const llvm::Triple &Triple) {<br> switch (Triple.getArch()) {<br>@@ -1304,6 +1324,9 @@ static std::string getCPUName(const ArgL<br> default:<br> return "";<br><br>+ case llvm::Triple::aarch64:<br>+ return getAArch64TargetCPU(Args, T);<br>+<br> case llvm::Triple::arm:<br> case llvm::Triple::thumb:<br> return getARMTargetCPU(Args, T);<br><br>Modified: cfe/trunk/lib/Driver/Tools.h<br>URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.h?rev=193740&r1=193739&r2=193740&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Tools.h?rev=193740&r1=193739&r2=193740&view=diff</a><br>==============================================================================<br>--- cfe/trunk/lib/Driver/Tools.h (original)<br>+++ cfe/trunk/lib/Driver/Tools.h Thu Oct 31 04:32:33 2013<br>@@ -49,6 +49,8 @@ using llvm::opt::ArgStringList;<br> const InputInfo &Output,<br> const InputInfoList &Inputs) const;<br><br>+ void AddAArch64TargetArgs(const llvm::opt::ArgList &Args,<br>+ llvm::opt::ArgStringList &CmdArgs) const;<br> void AddARMTargetArgs(const llvm::opt::ArgList &Args,<br> llvm::opt::ArgStringList &CmdArgs,<br> bool KernelOrKext) const;<br><br>Added: cfe/trunk/test/Driver/aarch64-cpus.c<br>URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=193740&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=193740&view=auto</a><br>==============================================================================<br>--- cfe/trunk/test/Driver/aarch64-cpus.c (added)<br>+++ cfe/trunk/test/Driver/aarch64-cpus.c Thu Oct 31 04:32:33 2013<br>@@ -0,0 +1,10 @@<br>+// Check target CPUs are correctly passed.<br>+<br>+// RUN: %clang -target aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=GENERIC %s<br>+// GENERIC: "-cc1"{{.*}} "-triple" "aarch64" {{.*}} "-target-cpu" "generic"<br>+<br>+// RUN: %clang -target aarch64 -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CA53 %s<br>+// CA53: "-cc1"{{.*}} "-triple" "aarch64" {{.*}} "-target-cpu" "cortex-a53"<br>+<br>+// RUN: %clang -target aarch64 -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57 %s<br>+// CA57: "-cc1"{{.*}} "-triple" "aarch64" {{.*}} "-target-cpu" "cortex-a57"<br><br>Added: cfe/trunk/test/Driver/aarch64-mfpu.c<br>URL: <a href="http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-mfpu.c?rev=193740&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-mfpu.c?rev=193740&view=auto</a><br>==============================================================================<br>--- cfe/trunk/test/Driver/aarch64-mfpu.c (added)<br>+++ cfe/trunk/test/Driver/aarch64-mfpu.c Thu Oct 31 04:32:33 2013<br>@@ -0,0 +1,26 @@<br>+// Test that different values of -mfpu pick correct AArch64 FPU target-feature(s).<br>+<br>+// RUN: %clang -target aarch64-linux-eabi -mfpu=neon %s -### -o %t.o 2>&1 \<br>+// RUN: | FileCheck --check-prefix=CHECK-NEON %s<br>+// CHECK-NEON: "-target-feature" "+neon"<br>+<br>+// RUN: %clang -target aarch64-linux-eabi -mfpu=fp-armv8 %s -### -o %t.o 2>&1 \<br>+// RUN: | FileCheck --check-prefix=CHECK-FP-ARMV8 %s<br>+// CHECK-FP-ARMV8: "-target-feature" "+fp-armv8"<br>+<br>+// RUN: %clang -target aarch64-linux-eabi -mfpu=neon-fp-armv8 %s -### 2>&1 \<br>+// RUN: | FileCheck --check-prefix=CHECK-NEON-FP-ARMV8 %s<br>+// CHECK-NEON-FP-ARMV8: "-target-feature" "+fp-armv8"<br>+// CHECK-NEON-FP-ARMV8: "-target-feature" "+neon"<br>+<br>+// RUN: %clang -target aarch64-linux-eabi -mfpu=crypto-neon-fp-armv8 %s -### 2>&1 \<br>+// RUN: | FileCheck --check-prefix=CHECK-CRYPTO-NEON-FP-ARMV8 %s<br>+// CHECK-CRYPTO-NEON-FP-ARMV8: "-target-feature" "+fp-armv8"<br>+// CHECK-CRYPTO-NEON-FP-ARMV8: "-target-feature" "+neon"<br>+// CHECK-CRYPTO-NEON-FP-ARMV8: "-target-feature" "+crypto"<br>+<br>+// RUN: %clang -target aarch64-linux-eabi -mfpu=none %s -### 2>&1 \<br>+// RUN: | FileCheck --check-prefix=CHECK-NO-FP %s<br>+// CHECK-NO-FP: "-target-feature" "-fp-armv8"<br>+// CHECK-NO-FP: "-target-feature" "-crypto"<br>+// CHECK-NO-FP: "-target-feature" "-neon"<br><br><br>_______________________________________________<br>cfe-commits mailing list<br><a href="mailto:cfe-commits@cs.uiuc.edu" target="_blank">cfe-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits</a><o:p></o:p></p></div><p class=MsoNormal style='mso-margin-top-alt:auto;mso-margin-bottom-alt:auto'> <o:p></o:p></p></div></div></div></div></div></div></blockquote></div><p class=MsoNormal><o:p> </o:p></p></div></div></div></div></body></html>