[PATCH] D34454: SwiftCC: Perform physical layout when computing coercion types

[Arnold Schwaighofer via Phabricator via cfe-commits]

aschwaighofer updated this revision to Diff 103458.
aschwaighofer retitled this revision from "SwiftAggregateLowering: Use type alloc size to determine the size of types" to "SwiftCC: Perform physical layout when computing coercion  types".
aschwaighofer edited the summary of this revision.
aschwaighofer removed a reviewer: cfe-commits.
aschwaighofer added a subscriber: cfe-commits.
aschwaighofer added a comment.

Based on email conversation with John. He pointed out we purposely don't want to use the allocation size for the algorithm and that we can just use LLVM's layout when we compute the coercion types.


https://reviews.llvm.org/D34454

Files:
  lib/CodeGen/SwiftCallingConv.cpp
  test/CodeGen/64bit-swiftcall.c


Index: test/CodeGen/64bit-swiftcall.c
===================================================================
--- test/CodeGen/64bit-swiftcall.c
+++ test/CodeGen/64bit-swiftcall.c
@@ -1,4 +1,5 @@
 // RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=X86-64
 // RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64
 
@@ -1014,3 +1015,20 @@
 TEST(struct_v1f3)
 // ARM64-LABEL: define swiftcc { <2 x float>, float } @return_struct_v1f3()
 // ARM64-LABEL: define swiftcc void @take_struct_v1f3(<2 x float>, float)
+
+typedef struct {
+  int3 vect;
+  unsigned long long val;
+} __attribute__((packed)) padded_alloc_size_vector;
+TEST(padded_alloc_size_vector)
+// X86-64-LABEL: take_padded_alloc_size_vector(<3 x i32>, i64)
+// X86-64-NOT: [4 x i8]
+// x86-64: ret void
+
+typedef union {
+  float f1;
+  float3 fv2;
+} union_hom_fp_partial2;
+TEST(union_hom_fp_partial2)
+// X86-64-LABEL: take_union_hom_fp_partial2(i64, float)
+// ARM64-LABEL: take_union_hom_fp_partial2(i64, float)
Index: lib/CodeGen/SwiftCallingConv.cpp
===================================================================
--- lib/CodeGen/SwiftCallingConv.cpp
+++ lib/CodeGen/SwiftCallingConv.cpp
@@ -57,6 +57,10 @@
   return CharUnits::fromQuantity(CGM.getDataLayout().getTypeStoreSize(type));
 }
 
+static CharUnits getTypeAllocSize(CodeGenModule &CGM, llvm::Type *type) {
+  return CharUnits::fromQuantity(CGM.getDataLayout().getTypeAllocSize(type));
+}
+
 void SwiftAggLowering::addTypedData(QualType type, CharUnits begin) {
   // Deal with various aggregate types as special cases:
 
@@ -542,7 +546,9 @@
       packed = true;
 
     elts.push_back(entry.Type);
-    lastEnd = entry.End;
+
+    lastEnd = entry.Begin + getTypeAllocSize(CGM, entry.Type);
+    assert(entry.End <= lastEnd);
   }
 
   // We don't need to adjust 'packed' to deal with possible tail padding


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